From mboxrd@z Thu Jan 1 00:00:00 1970 From: Borislav Petkov Subject: Re: [PATCH v6 03/16] x86/cpu/mtrr: Support TOP_MEM2 and get MTRR number Date: Mon, 10 Sep 2018 20:06:13 +0200 Message-ID: <20180910180613.GE4386@zn.tnic> References: Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Pu Wen Cc: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, thomas.lendacky@amd.com, pbonzini@redhat.com, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org List-Id: linux-arch.vger.kernel.org On Mon, Sep 10, 2018 at 09:16:03PM +0800, Pu Wen wrote: > The Hygon Dhyana CPU have a special magic MSR way to force WB for >From the last review round: Also, it is "The ... CPU has a special..." Please take your time and incorporate *all* review feedback - no need to *rush* a new revision out and drop review feedback. > memory >4GB, and support TOP_MEM2. Therefore, it is necessary to > add Hygon Dhyana support in amd_special_default_mtrr(). > > The number of variable MTRRs for Hygon is 2 as AMD's. > > Signed-off-by: Pu Wen > --- > arch/x86/kernel/cpu/mtrr/cleanup.c | 3 ++- > arch/x86/kernel/cpu/mtrr/mtrr.c | 2 +- > 2 files changed, 3 insertions(+), 2 deletions(-) With that fixed: Reviewed-by: Borislav Petkov -- Regards/Gruss, Boris. Good mailing practices for 400: avoid top-posting and trim the reply. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail.skyhub.de ([5.9.137.197]:34935 "EHLO mail.skyhub.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726709AbeIJXBh (ORCPT ); Mon, 10 Sep 2018 19:01:37 -0400 Date: Mon, 10 Sep 2018 20:06:13 +0200 From: Borislav Petkov Subject: Re: [PATCH v6 03/16] x86/cpu/mtrr: Support TOP_MEM2 and get MTRR number Message-ID: <20180910180613.GE4386@zn.tnic> References: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: Sender: linux-arch-owner@vger.kernel.org List-ID: To: Pu Wen Cc: tglx@linutronix.de, mingo@redhat.com, hpa@zytor.com, x86@kernel.org, thomas.lendacky@amd.com, pbonzini@redhat.com, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org Message-ID: <20180910180613.dvnXtHC67EgzZ7Wfg-yWzxJFiy9StQ3G7Gz7Q3ox4-c@z> On Mon, Sep 10, 2018 at 09:16:03PM +0800, Pu Wen wrote: > The Hygon Dhyana CPU have a special magic MSR way to force WB for