From mboxrd@z Thu Jan 1 00:00:00 1970 From: Sean Christopherson Subject: Re: RFC: userspace exception fixups Date: Fri, 2 Nov 2018 10:33:50 -0700 Message-ID: <20181102173350.GF7393@linux.intel.com> References: <20181101185225.GC5150@brightrain.aerifal.cx> <20181101193107.GE5150@brightrain.aerifal.cx> <20181102163034.GB7393@linux.intel.com> <7050972d-a874-dc08-3214-93e81181da60@intel.com> <20181102170627.GD7393@linux.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Dave Hansen Cc: Andy Lutomirski , Linus Torvalds , Rich Felker , Jann Horn , Dave Hansen , Jethro Beekman , Jarkko Sakkinen , Florian Weimer , Linux API , X86 ML , linux-arch , LKML , Peter Zijlstra , nhorman@redhat.com, npmccallum@redhat.com, "Ayoun, Serge" , shay.katz-zamir@intel.com, linux-sgx@vger.kernel.org, Andy Shevchenko , Thomas Gleixner , Ingo Molnar , Borislav Petkov List-Id: linux-arch.vger.kernel.org On Fri, Nov 02, 2018 at 10:13:23AM -0700, Dave Hansen wrote: > On 11/2/18 10:06 AM, Sean Christopherson wrote: > > On Fri, Nov 02, 2018 at 09:56:44AM -0700, Dave Hansen wrote: > >> On 11/2/18 9:30 AM, Sean Christopherson wrote: > >>> What if rather than having userspace register an address for fixup, the > >>> kernel instead unconditionally does fixup on the ENCLU opcode? > >> > >> The problem is knowing what to do for the fixup. If we have a simple > >> action to take that's universal, like backing up %RIP, or setting some > >> other register state, it's not bad. > > > > Isn't the EENTER/RESUME behavior universal? Or am I missing something? > > Could someone write down all the ways we get in and out of the enclave? > > I think we always get in from userspace calling EENTER or ERESUME. We > can't ever enter directly from the kernel, like via an IRET from what I > understand. Correct, the only way to get into the enclave is EENTER or ERESUME. My understanding is that even SMIs bounce through the AEX target before transitioning to SMM. > We get *out* from exceptions, hardware interrupts, or enclave-explicit > EEXITs. Did I miss any? Remind me where the hardware lands the control > flow in each of those exit cases. And VMExits. There are basically two cases: EEXIT and everything else. EEXIT is a glorified indirect jump, e.g. %RBX holds the target %RIP. Everything else is an Asynchronous Enclave Exit (AEX). On an AEX, %RIP is set to a value specified by EENTER/ERESUME, %RBP and %RSP are restored to pre-enclave values and all other registers are loaded with synthetic state. The actual interrupt/exception/VMExit then triggers, e.g. the %RIP on the stack for an exception is always the AEX target, not the %RIP inside the enclave that actually faulted. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com ([134.134.136.65]:38026 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726707AbeKCClr (ORCPT ); Fri, 2 Nov 2018 22:41:47 -0400 Date: Fri, 2 Nov 2018 10:33:50 -0700 From: Sean Christopherson Subject: Re: RFC: userspace exception fixups Message-ID: <20181102173350.GF7393@linux.intel.com> References: <20181101185225.GC5150@brightrain.aerifal.cx> <20181101193107.GE5150@brightrain.aerifal.cx> <20181102163034.GB7393@linux.intel.com> <7050972d-a874-dc08-3214-93e81181da60@intel.com> <20181102170627.GD7393@linux.intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Sender: linux-arch-owner@vger.kernel.org List-ID: To: Dave Hansen Cc: Andy Lutomirski , Linus Torvalds , Rich Felker , Jann Horn , Dave Hansen , Jethro Beekman , Jarkko Sakkinen , Florian Weimer , Linux API , X86 ML , linux-arch , LKML , Peter Zijlstra , nhorman@redhat.com, npmccallum@redhat.com, "Ayoun, Serge" , shay.katz-zamir@intel.com, linux-sgx@vger.kernel.org, Andy Shevchenko , Thomas Gleixner , Ingo Molnar , Borislav Petkov , Carlos O'Donell , adhemerval.zanella@linaro.org Message-ID: <20181102173350.ZMsKV_dFpN9Mp5nL3IXswXeyBgzX4lKe05SfvYj46q0@z> On Fri, Nov 02, 2018 at 10:13:23AM -0700, Dave Hansen wrote: > On 11/2/18 10:06 AM, Sean Christopherson wrote: > > On Fri, Nov 02, 2018 at 09:56:44AM -0700, Dave Hansen wrote: > >> On 11/2/18 9:30 AM, Sean Christopherson wrote: > >>> What if rather than having userspace register an address for fixup, the > >>> kernel instead unconditionally does fixup on the ENCLU opcode? > >> > >> The problem is knowing what to do for the fixup. If we have a simple > >> action to take that's universal, like backing up %RIP, or setting some > >> other register state, it's not bad. > > > > Isn't the EENTER/RESUME behavior universal? Or am I missing something? > > Could someone write down all the ways we get in and out of the enclave? > > I think we always get in from userspace calling EENTER or ERESUME. We > can't ever enter directly from the kernel, like via an IRET from what I > understand. Correct, the only way to get into the enclave is EENTER or ERESUME. My understanding is that even SMIs bounce through the AEX target before transitioning to SMM. > We get *out* from exceptions, hardware interrupts, or enclave-explicit > EEXITs. Did I miss any? Remind me where the hardware lands the control > flow in each of those exit cases. And VMExits. There are basically two cases: EEXIT and everything else. EEXIT is a glorified indirect jump, e.g. %RBX holds the target %RIP. Everything else is an Asynchronous Enclave Exit (AEX). On an AEX, %RIP is set to a value specified by EENTER/ERESUME, %RBP and %RSP are restored to pre-enclave values and all other registers are loaded with synthetic state. The actual interrupt/exception/VMExit then triggers, e.g. the %RIP on the stack for an exception is always the AEX target, not the %RIP inside the enclave that actually faulted.