From mboxrd@z Thu Jan 1 00:00:00 1970 From: Peter Zijlstra Subject: Re: 1808d65b55 ("asm-generic/tlb: Remove arch_tlb*_mmu()"): BUG: KASAN: stack-out-of-bounds in __change_page_attr_set_clr Date: Fri, 12 Apr 2019 20:15:57 +0200 Message-ID: <20190412181557.GC12232@hirez.programming.kicks-ass.net> References: <5cae03c4.iIPk2cWlfmzP0Zgy%lkp@intel.com> <20190411193906.GA12232@hirez.programming.kicks-ass.net> <20190411195424.GL14281@hirez.programming.kicks-ass.net> <20190411211348.GA8451@worktop.programming.kicks-ass.net> <20190412105633.GM14281@hirez.programming.kicks-ass.net> <5890.1555087830@warthog.procyon.org.uk> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <5890.1555087830@warthog.procyon.org.uk> Sender: linux-kernel-owner@vger.kernel.org To: David Howells Cc: Linus Torvalds , kernel test robot , LKP , Linux List Kernel Mailing , Linux-MM , linux-arch , Ingo Molnar , Thomas Gleixner , Will Deacon , Andy Lutomirski , Nadav Amit List-Id: linux-arch.vger.kernel.org On Fri, Apr 12, 2019 at 05:50:30PM +0100, David Howells wrote: > Linus Torvalds wrote: > > > We should never have stack alignment bigger than 16 bytes. And > > preferably not even that. > > At least one arch I know of (FRV) had instructions that could atomically > load/store register pairs or register quads, but they had to be pair- or > quad-aligned (ie. 8- or 16-byte), which made for more efficient code if you > could use them. > > I don't know whether any arch we currently support has features like this (I > know some have multi-reg load/stores, but they seem to require only > word-alignment). ARC (iirc) has u64 atomics with natural alignment requirements but alignof(u64)=4 due it being a 32bit arch. Which is awkward. ARMv7 can also do u64 ops when aligned right, but I forgot if they have proper alignment or not. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from bombadil.infradead.org ([198.137.202.133]:55670 "EHLO bombadil.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726797AbfDLSQG (ORCPT ); Fri, 12 Apr 2019 14:16:06 -0400 Date: Fri, 12 Apr 2019 20:15:57 +0200 From: Peter Zijlstra Subject: Re: 1808d65b55 ("asm-generic/tlb: Remove arch_tlb*_mmu()"): BUG: KASAN: stack-out-of-bounds in __change_page_attr_set_clr Message-ID: <20190412181557.GC12232@hirez.programming.kicks-ass.net> References: <5cae03c4.iIPk2cWlfmzP0Zgy%lkp@intel.com> <20190411193906.GA12232@hirez.programming.kicks-ass.net> <20190411195424.GL14281@hirez.programming.kicks-ass.net> <20190411211348.GA8451@worktop.programming.kicks-ass.net> <20190412105633.GM14281@hirez.programming.kicks-ass.net> <5890.1555087830@warthog.procyon.org.uk> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <5890.1555087830@warthog.procyon.org.uk> Sender: linux-arch-owner@vger.kernel.org List-ID: To: David Howells Cc: Linus Torvalds , kernel test robot , LKP , Linux List Kernel Mailing , Linux-MM , linux-arch , Ingo Molnar , Thomas Gleixner , Will Deacon , Andy Lutomirski , Nadav Amit Message-ID: <20190412181557.GGr4QhgDT3QDF9O-OCbRJBi9dYB4ugZdbejv0YRFuTo@z> On Fri, Apr 12, 2019 at 05:50:30PM +0100, David Howells wrote: > Linus Torvalds wrote: > > > We should never have stack alignment bigger than 16 bytes. And > > preferably not even that. > > At least one arch I know of (FRV) had instructions that could atomically > load/store register pairs or register quads, but they had to be pair- or > quad-aligned (ie. 8- or 16-byte), which made for more efficient code if you > could use them. > > I don't know whether any arch we currently support has features like this (I > know some have multi-reg load/stores, but they seem to require only > word-alignment). ARC (iirc) has u64 atomics with natural alignment requirements but alignof(u64)=4 due it being a 32bit arch. Which is awkward. ARMv7 can also do u64 ops when aligned right, but I forgot if they have proper alignment or not.