From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christoph Hellwig Subject: Re: [PATCH] riscv: Support non-coherency memory model Date: Wed, 24 Apr 2019 16:23:06 +0200 Message-ID: <20190424142306.GB20974@lst.de> References: <1555947870-23014-1-git-send-email-guoren@kernel.org> <20190422161814.GA30694@lst.de> <20190423001348.GA31639@guoren-Inspiron-7460> <20190423055548.GA12365@lst.de> <20190423154642.GA16001@guoren-Inspiron-7460> <20190424020803.GA27332@guoren-Inspiron-7460> <20190424055703.GA3417@guoren-Inspiron-7460> <4e6b0816-3fe9-8c0b-a749-f7f6ef7e5742@garyguo.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: <4e6b0816-3fe9-8c0b-a749-f7f6ef7e5742@garyguo.net> Sender: linux-kernel-owner@vger.kernel.org To: Gary Guo Cc: Guo Ren , Christoph Hellwig , "linux-arch@vger.kernel.org" , Palmer Dabbelt , Andrew Waterman , Arnd Bergmann , Anup Patel , Xiang Xiaoyan , "linux-kernel@vger.kernel.org" , Mike Rapoport , Vincent Chen , Greentime Hu , "ren_guo@c-sky.com" , "linux-riscv@lists.infradead.org" , Marek Szyprowski , Robin Murphy , Scott Wood , "tech-privileged@lists.riscv.org" List-Id: linux-arch.vger.kernel.org On Wed, Apr 24, 2019 at 12:45:56PM +0000, Gary Guo wrote: > The RISC-V privileged spec is explicitly designed to allow the > techniques described above (this is the sole purpose of MSTATUS.TVM). It > might be as high performance as a hardware with H-extension, but is > definitely a legit use case. In fact, it is vital for use cases like > recursive virtualization. > > Also, I believe the PTE format of RISC-V is already frozen -- therefore > it is impossible now to merge GLOBAL and USER bit, nor to replace RSW > bit with another bit. Yes, I do not think we can just repurpose a bit. Even using a currently unused one would require some gymnastics. That being said IFF we want to support non-coherent DMA (and I think we do as people glue together their SOCs using shoestring and paper clips, as already demonstrated by Andes and C-SKY in RISC-V space, and most arm, mips and ppc SOCs) we need something like this flag. The current RISC-V method that only allows M-mode to set up such attributes on a small number or PMP regions just doesn't work well with the way how Linux and most non-trivial OSes implement DMA memory allocations. Note that I said well - in theory we can have a firmware provided uncached pool - that is what Linux does on most nommu (that is without pagetables) ports, but the fixed sized pool really does suck and will make users very unhappy. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from verein.lst.de ([213.95.11.211]:54144 "EHLO newverein.lst.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725921AbfDXOXY (ORCPT ); Wed, 24 Apr 2019 10:23:24 -0400 Date: Wed, 24 Apr 2019 16:23:06 +0200 From: Christoph Hellwig Subject: Re: [PATCH] riscv: Support non-coherency memory model Message-ID: <20190424142306.GB20974@lst.de> References: <1555947870-23014-1-git-send-email-guoren@kernel.org> <20190422161814.GA30694@lst.de> <20190423001348.GA31639@guoren-Inspiron-7460> <20190423055548.GA12365@lst.de> <20190423154642.GA16001@guoren-Inspiron-7460> <20190424020803.GA27332@guoren-Inspiron-7460> <20190424055703.GA3417@guoren-Inspiron-7460> <4e6b0816-3fe9-8c0b-a749-f7f6ef7e5742@garyguo.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <4e6b0816-3fe9-8c0b-a749-f7f6ef7e5742@garyguo.net> Sender: linux-arch-owner@vger.kernel.org List-ID: To: Gary Guo Cc: Guo Ren , Christoph Hellwig , "linux-arch@vger.kernel.org" , Palmer Dabbelt , Andrew Waterman , Arnd Bergmann , Anup Patel , Xiang Xiaoyan , "linux-kernel@vger.kernel.org" , Mike Rapoport , Vincent Chen , Greentime Hu , "ren_guo@c-sky.com" , "linux-riscv@lists.infradead.org" , Marek Szyprowski , Robin Murphy , Scott Wood , "tech-privileged@lists.riscv.org" Message-ID: <20190424142306.KnhJ2grbWPnRYvCMi8Vx-BAbb9hCHeowvobuhcYqWoE@z> On Wed, Apr 24, 2019 at 12:45:56PM +0000, Gary Guo wrote: > The RISC-V privileged spec is explicitly designed to allow the > techniques described above (this is the sole purpose of MSTATUS.TVM). It > might be as high performance as a hardware with H-extension, but is > definitely a legit use case. In fact, it is vital for use cases like > recursive virtualization. > > Also, I believe the PTE format of RISC-V is already frozen -- therefore > it is impossible now to merge GLOBAL and USER bit, nor to replace RSW > bit with another bit. Yes, I do not think we can just repurpose a bit. Even using a currently unused one would require some gymnastics. That being said IFF we want to support non-coherent DMA (and I think we do as people glue together their SOCs using shoestring and paper clips, as already demonstrated by Andes and C-SKY in RISC-V space, and most arm, mips and ppc SOCs) we need something like this flag. The current RISC-V method that only allows M-mode to set up such attributes on a small number or PMP regions just doesn't work well with the way how Linux and most non-trivial OSes implement DMA memory allocations. Note that I said well - in theory we can have a firmware provided uncached pool - that is what Linux does on most nommu (that is without pagetables) ports, but the fixed sized pool really does suck and will make users very unhappy.