From mboxrd@z Thu Jan 1 00:00:00 1970 From: Peter Zijlstra Subject: Re: [PATCH 3/3] asm-generic, x86: Add bitops instrumentation for KASAN Date: Wed, 29 May 2019 12:30:10 +0200 Message-ID: <20190529103010.GP2623@hirez.programming.kicks-ass.net> References: <20190528163258.260144-1-elver@google.com> <20190528163258.260144-3-elver@google.com> <20190528165036.GC28492@lakrids.cambridge.arm.com> <20190529100116.GM2623@hirez.programming.kicks-ass.net> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Content-Disposition: inline In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Marco Elver Cc: Dmitry Vyukov , Mark Rutland , Andrey Ryabinin , Alexander Potapenko , Andrey Konovalov , Jonathan Corbet , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , the arch/x86 maintainers , Arnd Bergmann , Josh Poimboeuf , "open list:DOCUMENTATION" , LKML , linux-arch , kasan-dev List-Id: linux-arch.vger.kernel.org On Wed, May 29, 2019 at 12:16:31PM +0200, Marco Elver wrote: > On Wed, 29 May 2019 at 12:01, Peter Zijlstra wrote: > > > > On Wed, May 29, 2019 at 11:20:17AM +0200, Marco Elver wrote: > > > For the default, we decided to err on the conservative side for now, > > > since it seems that e.g. x86 operates only on the byte the bit is on. > > > > This is not correct, see for instance set_bit(): > > > > static __always_inline void > > set_bit(long nr, volatile unsigned long *addr) > > { > > if (IS_IMMEDIATE(nr)) { > > asm volatile(LOCK_PREFIX "orb %1,%0" > > : CONST_MASK_ADDR(nr, addr) > > : "iq" ((u8)CONST_MASK(nr)) > > : "memory"); > > } else { > > asm volatile(LOCK_PREFIX __ASM_SIZE(bts) " %1,%0" > > : : RLONG_ADDR(addr), "Ir" (nr) : "memory"); > > } > > } > > > > That results in: > > > > LOCK BTSQ nr, (addr) > > > > when @nr is not an immediate. > > Thanks for the clarification. Given that arm64 already instruments > bitops access to whole words, and x86 may also do so for some bitops, > it seems fine to instrument word-sized accesses by default. Is that > reasonable? Eminently -- the API is defined such; for bonus points KASAN should also do alignment checks on atomic ops. Future hardware will #AC on unaligned [*] LOCK prefix instructions. (*) not entirely accurate, it will only trap when crossing a line. https://lkml.kernel.org/r/1556134382-58814-1-git-send-email-fenghua.yu@intel.com From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from merlin.infradead.org ([205.233.59.134]:33956 "EHLO merlin.infradead.org" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1725990AbfE2Kad (ORCPT ); Wed, 29 May 2019 06:30:33 -0400 Date: Wed, 29 May 2019 12:30:10 +0200 From: Peter Zijlstra Subject: Re: [PATCH 3/3] asm-generic, x86: Add bitops instrumentation for KASAN Message-ID: <20190529103010.GP2623@hirez.programming.kicks-ass.net> References: <20190528163258.260144-1-elver@google.com> <20190528163258.260144-3-elver@google.com> <20190528165036.GC28492@lakrids.cambridge.arm.com> <20190529100116.GM2623@hirez.programming.kicks-ass.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Sender: linux-arch-owner@vger.kernel.org List-ID: To: Marco Elver Cc: Dmitry Vyukov , Mark Rutland , Andrey Ryabinin , Alexander Potapenko , Andrey Konovalov , Jonathan Corbet , Thomas Gleixner , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , the arch/x86 maintainers , Arnd Bergmann , Josh Poimboeuf , "open list:DOCUMENTATION" , LKML , linux-arch , kasan-dev Message-ID: <20190529103010.FWLCIh5v4erAH6MtRLMn8gItXXf-SGNAcBvflYQgYnE@z> On Wed, May 29, 2019 at 12:16:31PM +0200, Marco Elver wrote: > On Wed, 29 May 2019 at 12:01, Peter Zijlstra wrote: > > > > On Wed, May 29, 2019 at 11:20:17AM +0200, Marco Elver wrote: > > > For the default, we decided to err on the conservative side for now, > > > since it seems that e.g. x86 operates only on the byte the bit is on. > > > > This is not correct, see for instance set_bit(): > > > > static __always_inline void > > set_bit(long nr, volatile unsigned long *addr) > > { > > if (IS_IMMEDIATE(nr)) { > > asm volatile(LOCK_PREFIX "orb %1,%0" > > : CONST_MASK_ADDR(nr, addr) > > : "iq" ((u8)CONST_MASK(nr)) > > : "memory"); > > } else { > > asm volatile(LOCK_PREFIX __ASM_SIZE(bts) " %1,%0" > > : : RLONG_ADDR(addr), "Ir" (nr) : "memory"); > > } > > } > > > > That results in: > > > > LOCK BTSQ nr, (addr) > > > > when @nr is not an immediate. > > Thanks for the clarification. Given that arm64 already instruments > bitops access to whole words, and x86 may also do so for some bitops, > it seems fine to instrument word-sized accesses by default. Is that > reasonable? Eminently -- the API is defined such; for bonus points KASAN should also do alignment checks on atomic ops. Future hardware will #AC on unaligned [*] LOCK prefix instructions. (*) not entirely accurate, it will only trap when crossing a line. https://lkml.kernel.org/r/1556134382-58814-1-git-send-email-fenghua.yu@intel.com