From mboxrd@z Thu Jan 1 00:00:00 1970 From: Christoph Hellwig Subject: Re: [PATCH v1 1/6] arm64: Detect the ARMv8.4 TTL feature Date: Tue, 21 Apr 2020 10:16:41 -0700 Message-ID: <20200421171641.GA25391@infradead.org> References: <20200403090048.938-1-yezhenyu2@huawei.com> <20200403090048.938-2-yezhenyu2@huawei.com> <20200421165346.GA11171@infradead.org> <20200421171328.GW20730@hirez.programming.kicks-ass.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: Content-Disposition: inline In-Reply-To: <20200421171328.GW20730@hirez.programming.kicks-ass.net> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: "linux-arm-kernel" Errors-To: linux-arm-kernel-bounces+linux-arm-kernel=m.gmane-mx.org@lists.infradead.org To: Peter Zijlstra Cc: mark.rutland@arm.com, catalin.marinas@arm.com, linux-mm@kvack.org, guohanjun@huawei.com, will@kernel.org, linux-arch@vger.kernel.org, yuzhao@google.com, maz@kernel.org, suzuki.poulose@arm.com, steven.price@arm.com, Christoph Hellwig , arm@kernel.org, Dave.Martin@arm.com, arnd@arndb.de, Zhenyu Ye , npiggin@gmail.com, zhangshaokun@hisilicon.com, broonie@kernel.org, rostedt@goodmis.org, prime.zeng@hisilicon.com, kuhn.chenqun@huawei.com, tglx@linutronix.de, linux-arm-kernel@lists.infradead.org, xiexiangyou@huawei.com, linux-kernel@vger.kernel.org, aneesh.kumar@linux.ibm.com, akpm@linux-foundation.org List-Id: linux-arch.vger.kernel.org On Tue, Apr 21, 2020 at 07:13:28PM +0200, Peter Zijlstra wrote: > On Tue, Apr 21, 2020 at 09:53:46AM -0700, Christoph Hellwig wrote: > > On Fri, Apr 03, 2020 at 05:00:43PM +0800, Zhenyu Ye wrote: > > > From: Marc Zyngier > > > > > > In order to reduce the cost of TLB invalidation, the ARMv8.4 TTL > > > feature allows TLBs to be issued with a level allowing for quicker > > > invalidation. > > > > What does "issued with a level" mean? > > What I understood it to be is page-size based on page-table hierarchy. > Just like we have on x86, 4k, 2m, 1g etc.. > > So where x86 INVLPG will tear down any sized page for the address given, > you can now day, kill me the PMD level translation for @addr. > > Power9 radix also has things like this. Maybe this needs to be spelled out a little more? The current commit log sounds like paper generated by a neural network. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from lindbergh.monkeyblade.net ([23.128.96.19]:46364 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-FAIL-OK-FAIL) by vger.kernel.org with ESMTP id S1726878AbgDURQ6 (ORCPT ); Tue, 21 Apr 2020 13:16:58 -0400 Date: Tue, 21 Apr 2020 10:16:41 -0700 From: Christoph Hellwig Subject: Re: [PATCH v1 1/6] arm64: Detect the ARMv8.4 TTL feature Message-ID: <20200421171641.GA25391@infradead.org> References: <20200403090048.938-1-yezhenyu2@huawei.com> <20200403090048.938-2-yezhenyu2@huawei.com> <20200421165346.GA11171@infradead.org> <20200421171328.GW20730@hirez.programming.kicks-ass.net> MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20200421171328.GW20730@hirez.programming.kicks-ass.net> Sender: linux-arch-owner@vger.kernel.org List-ID: To: Peter Zijlstra Cc: Christoph Hellwig , Zhenyu Ye , mark.rutland@arm.com, will@kernel.org, catalin.marinas@arm.com, aneesh.kumar@linux.ibm.com, akpm@linux-foundation.org, npiggin@gmail.com, arnd@arndb.de, rostedt@goodmis.org, maz@kernel.org, suzuki.poulose@arm.com, tglx@linutronix.de, yuzhao@google.com, Dave.Martin@arm.com, steven.price@arm.com, broonie@kernel.org, guohanjun@huawei.com, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, xiexiangyou@huawei.com, zhangshaokun@hisilicon.com, linux-mm@kvack.org, arm@kernel.org, prime.zeng@hisilicon.com, kuhn.chenqun@huawei.com, linux-arm-kernel@lists.infradead.org Message-ID: <20200421171641.ymxoirfi_R2PpPW96XLh01Y25yd-HThZh2SaiL5XYVM@z> On Tue, Apr 21, 2020 at 07:13:28PM +0200, Peter Zijlstra wrote: > On Tue, Apr 21, 2020 at 09:53:46AM -0700, Christoph Hellwig wrote: > > On Fri, Apr 03, 2020 at 05:00:43PM +0800, Zhenyu Ye wrote: > > > From: Marc Zyngier > > > > > > In order to reduce the cost of TLB invalidation, the ARMv8.4 TTL > > > feature allows TLBs to be issued with a level allowing for quicker > > > invalidation. > > > > What does "issued with a level" mean? > > What I understood it to be is page-size based on page-table hierarchy. > Just like we have on x86, 4k, 2m, 1g etc.. > > So where x86 INVLPG will tear down any sized page for the address given, > you can now day, kill me the PMD level translation for @addr. > > Power9 radix also has things like this. Maybe this needs to be spelled out a little more? The current commit log sounds like paper generated by a neural network.