From mboxrd@z Thu Jan 1 00:00:00 1970 From: Catalin Marinas Subject: Re: [PATCH v2 2/6] arm64: Add level-hinted TLB invalidation helper Date: Fri, 22 May 2020 16:50:17 +0100 Message-ID: <20200522155017.GG26492@gaia> References: <20200423135656.2712-1-yezhenyu2@huawei.com> <20200423135656.2712-3-yezhenyu2@huawei.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Return-path: Received: from foss.arm.com ([217.140.110.172]:38456 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1730109AbgEVPu2 (ORCPT ); Fri, 22 May 2020 11:50:28 -0400 Content-Disposition: inline In-Reply-To: <20200423135656.2712-3-yezhenyu2@huawei.com> Sender: linux-arch-owner@vger.kernel.org List-ID: To: Zhenyu Ye Cc: peterz@infradead.org, mark.rutland@arm.com, will@kernel.org, aneesh.kumar@linux.ibm.com, akpm@linux-foundation.org, npiggin@gmail.com, arnd@arndb.de, rostedt@goodmis.org, maz@kernel.org, suzuki.poulose@arm.com, tglx@linutronix.de, yuzhao@google.com, Dave.Martin@arm.com, steven.price@arm.com, broonie@kernel.org, guohanjun@huawei.com, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-mm@kvack.org, arm@kernel.org, xiexiangyou@huawei.com, prime.zeng@hisilicon.com, zhangshaokun@hisilicon.com, kuhn.chenqun@huawei.com On Thu, Apr 23, 2020 at 09:56:52PM +0800, Zhenyu Ye wrote: > diff --git a/arch/arm64/include/asm/tlbflush.h b/arch/arm64/include/asm/tlbflush.h > index bc3949064725..5f9f189bc6d2 100644 > --- a/arch/arm64/include/asm/tlbflush.h > +++ b/arch/arm64/include/asm/tlbflush.h > @@ -10,6 +10,7 @@ > > #ifndef __ASSEMBLY__ > > +#include > #include > #include > #include > @@ -59,6 +60,35 @@ > __ta; \ > }) > > +#define TLBI_TTL_MASK GENMASK_ULL(47, 44) > + > +#define __tlbi_level(op, addr, level) \ > + do { \ Nitpick: move "do {" on the same line as __tlbi_level() to reduce the indentation levels of the whole block. Reviewed-by: Catalin Marinas