From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org X-Spam-Level: X-Spam-Status: No, score=-8.8 required=3.0 tests=BAYES_00, HEADER_FROM_DIFFERENT_DOMAINS,INCLUDES_PATCH,MAILING_LIST_MULTI,SPF_HELO_NONE, SPF_PASS autolearn=ham autolearn_force=no version=3.4.0 Received: from mail.kernel.org (mail.kernel.org [198.145.29.99]) by smtp.lore.kernel.org (Postfix) with ESMTP id 05C1AC64E7B for ; Wed, 2 Dec 2020 18:09:45 +0000 (UTC) Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by mail.kernel.org (Postfix) with ESMTP id 9B73C221FC for ; Wed, 2 Dec 2020 18:09:44 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S1728631AbgLBSJS (ORCPT ); Wed, 2 Dec 2020 13:09:18 -0500 Received: from foss.arm.com ([217.140.110.172]:46930 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1727108AbgLBSJS (ORCPT ); Wed, 2 Dec 2020 13:09:18 -0500 Received: from usa-sjc-imap-foss1.foss.arm.com (unknown [10.121.207.14]) by usa-sjc-mx-foss1.foss.arm.com (Postfix) with ESMTP id 6BB1E1042; Wed, 2 Dec 2020 10:08:32 -0800 (PST) Received: from e107158-lin.cambridge.arm.com (unknown [10.1.194.78]) by usa-sjc-imap-foss1.foss.arm.com (Postfix) with ESMTPSA id 39D093F575; Wed, 2 Dec 2020 10:08:30 -0800 (PST) Date: Wed, 2 Dec 2020 18:08:27 +0000 From: Qais Yousef To: Will Deacon Cc: linux-arm-kernel@lists.infradead.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, Catalin Marinas , Marc Zyngier , Greg Kroah-Hartman , Peter Zijlstra , Morten Rasmussen , Suren Baghdasaryan , Quentin Perret , Tejun Heo , Li Zefan , Johannes Weiner , Ingo Molnar , Juri Lelli , Vincent Guittot , kernel-team@android.com Subject: Re: [PATCH v4 12/14] arm64: Prevent offlining first CPU with 32-bit EL0 on mismatched system Message-ID: <20201202180827.7thdjnpnvfxh3s3r@e107158-lin.cambridge.arm.com> References: <20201124155039.13804-1-will@kernel.org> <20201124155039.13804-13-will@kernel.org> <20201127134122.oughqeizhl2j4iky@e107158-lin.cambridge.arm.com> <20201201221335.GA28496@willie-the-truck> <20201202125952.z2q6oucoqbwt6aq2@e107158-lin.cambridge.arm.com> <20201202174230.GA29939@willie-the-truck> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline In-Reply-To: <20201202174230.GA29939@willie-the-truck> Precedence: bulk List-ID: X-Mailing-List: linux-arch@vger.kernel.org On 12/02/20 17:42, Will Deacon wrote: > On Wed, Dec 02, 2020 at 12:59:52PM +0000, Qais Yousef wrote: > > On 12/01/20 22:13, Will Deacon wrote: > > > On Fri, Nov 27, 2020 at 01:41:22PM +0000, Qais Yousef wrote: > > > > On 11/24/20 15:50, Will Deacon wrote: > > > > > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c > > > > > index 29017cbb6c8e..fe470683b43e 100644 > > > > > --- a/arch/arm64/kernel/cpufeature.c > > > > > +++ b/arch/arm64/kernel/cpufeature.c > > > > > @@ -1237,6 +1237,8 @@ has_cpuid_feature(const struct arm64_cpu_capabilities *entry, int scope) > > > > > > > > > > static int enable_mismatched_32bit_el0(unsigned int cpu) > > > > > { > > > > > + static int lucky_winner = -1; > > > > > + > > > > > struct cpuinfo_arm64 *info = &per_cpu(cpu_data, cpu); > > > > > bool cpu_32bit = id_aa64pfr0_32bit_el0(info->reg_id_aa64pfr0); > > > > > > > > > > @@ -1245,6 +1247,22 @@ static int enable_mismatched_32bit_el0(unsigned int cpu) > > > > > static_branch_enable_cpuslocked(&arm64_mismatched_32bit_el0); > > > > > } > > > > > > > > > > + if (cpumask_test_cpu(0, cpu_32bit_el0_mask) == cpu_32bit) > > > > > + return 0; > > > > > > > > Hmm I'm struggling to get what you're doing here. You're treating CPU0 (the > > > > boot CPU) specially here, but I don't get why? > > > > > > If our ability to execute 32-bit code is the same as the boot CPU then we > > > don't have to do anything. That way, we can postpone nominating the lucky > > > winner until we really need to. > > > > Okay I see what you're doing now. The '== cpu_32bit' part of the check gave me > > trouble. If the first N cpus are 64bit only, we'll skip them here. Worth > > a comment? > > > > Wouldn't it be better to replace this with a check if cpu_32bit_el0_mask is > > empty instead? That would be a lot easier to read. > > Sorry, but I don't follow. What if all the CPUs are 32-bit capable? You're right I missed this case. -- Qais Yousef