From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id 968F3C43334 for ; Mon, 6 Jun 2022 14:32:29 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S239723AbiFFOc0 (ORCPT ); Mon, 6 Jun 2022 10:32:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:47892 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S239627AbiFFOcZ (ORCPT ); Mon, 6 Jun 2022 10:32:25 -0400 Received: from mga03.intel.com (mga03.intel.com [134.134.136.65]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 4DB7619FB4; Mon, 6 Jun 2022 07:32:22 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=intel.com; i=@intel.com; q=dns/txt; s=Intel; t=1654525944; x=1686061944; h=from:to:cc:subject:date:message-id:in-reply-to: references:mime-version:content-transfer-encoding; bh=UxE8NFVyWkYcl6VDWo0Xc7AS/+WRnnbtxB431hbdf8E=; b=BICLIJM1RRUCHuX5r1LZbr9NC+T+7i63AocrimLUDszR/dCCi89tIQkF 5mXYjeKhFHeEvnHqrwDg+Jp4eU/uw+qrvz0lh8zr5Vatiw+8/bWTa9B2o I0bD2HMpA4B7RcvOqjq+UvXDNx3qDGBQUJK0ecrZB+g5nSpmiJfMNBYi+ aW22VdsYFlfiIbBlcT+K17FNEsy9E5DI0h8D2qTKDaSO6vCOl7NKQNQ6a pRqjzv16kzSegYarBS+O4/A5MivnXSkE3ObHjlZ84/8eFM////8/bdiZb xj4CZ8u3k8aKcMRRk+obDxVkgPJsjZht12QuKVpmUphsNBo7ZiiRTiE8S A==; X-IronPort-AV: E=McAfee;i="6400,9594,10369"; a="276980221" X-IronPort-AV: E=Sophos;i="5.91,280,1647327600"; d="scan'208";a="276980221" Received: from orsmga001.jf.intel.com ([10.7.209.18]) by orsmga103.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 06 Jun 2022 07:22:40 -0700 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.91,280,1647327600"; d="scan'208";a="614371881" Received: from irvmail001.ir.intel.com ([10.43.11.63]) by orsmga001.jf.intel.com with ESMTP; 06 Jun 2022 07:22:34 -0700 Received: from newjersey.igk.intel.com (newjersey.igk.intel.com [10.102.20.203]) by irvmail001.ir.intel.com (8.14.3/8.13.6/MailSET/Hub) with ESMTP id 256EMW5u012713; Mon, 6 Jun 2022 15:22:32 +0100 From: Alexander Lobakin To: Mark Rutland Cc: Alexander Lobakin , Arnd Bergmann , Yury Norov , "Andy Shevchenko" , Richard Henderson , Matt Turner , Brian Cain , Geert Uytterhoeven , "Yoshinori Sato" , Rich Felker , "David S. Miller" , Kees Cook , "Peter Zijlstra (Intel)" , Marco Elver , Borislav Petkov , Tony Luck , "Greg Kroah-Hartman" , linux-alpha@vger.kernel.org, linux-hexagon@vger.kernel.org, linux-ia64@vger.kernel.org, linux-m68k@lists.linux-m68k.org, linux-sh@vger.kernel.org, sparclinux@vger.kernel.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH 2/6] bitops: always define asm-generic non-atomic bitops Date: Mon, 6 Jun 2022 16:21:35 +0200 Message-Id: <20220606142135.965134-1-alexandr.lobakin@intel.com> X-Mailer: git-send-email 2.36.1 In-Reply-To: References: <20220606114908.962562-1-alexandr.lobakin@intel.com> <20220606114908.962562-3-alexandr.lobakin@intel.com> MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-arch@vger.kernel.org From: Mark Rutland Date: Mon, 6 Jun 2022 13:44:52 +0100 > On Mon, Jun 06, 2022 at 01:49:03PM +0200, Alexander Lobakin wrote: > > Move generic non-atomic bitops from the asm-generic header which > > gets included only when there are no architecture-specific > > alternatives, to a separate independent file to make them always > > available. > > > > Signed-off-by: Alexander Lobakin > > --- > > .../asm-generic/bitops/generic-non-atomic.h | 124 ++++++++++++++++++ > > include/asm-generic/bitops/non-atomic.h | 109 ++------------- > > 2 files changed, 132 insertions(+), 101 deletions(-) > > create mode 100644 include/asm-generic/bitops/generic-non-atomic.h > > > > diff --git a/include/asm-generic/bitops/generic-non-atomic.h b/include/asm-generic/bitops/generic-non-atomic.h > > new file mode 100644 > > index 000000000000..7a60adfa6e7d > > --- /dev/null > > +++ b/include/asm-generic/bitops/generic-non-atomic.h > > @@ -0,0 +1,124 @@ > > +/* SPDX-License-Identifier: GPL-2.0-only */ > > +#ifndef __ASM_GENERIC_BITOPS_GENERIC_NON_ATOMIC_H > > +#define __ASM_GENERIC_BITOPS_GENERIC_NON_ATOMIC_H > > + > > +#include > > + > > +#ifndef _LINUX_BITOPS_H > > +#error only can be included directly > > +#endif > > + > > +/* > > + * Generic definitions for bit operations, should not be used in regular code > > + * directly. > > + */ > > + > > +/** > > + * gen___set_bit - Set a bit in memory > > + * @nr: the bit to set > > + * @addr: the address to start counting from > > + * > > + * Unlike set_bit(), this function is non-atomic and may be reordered. > > + * If it's called on the same region of memory simultaneously, the effect > > + * may be that only one operation succeeds. > > + */ > > +static __always_inline void > > +gen___set_bit(unsigned int nr, volatile unsigned long *addr) > > Could we please use 'generic' rather than 'gen' as the prefix? > > That'd match what we did for the generic atomic_*() and atomic64_*() functions > in commits > > * f8b6455a9d381fc5 ("locking/atomic: atomic: support ARCH_ATOMIC") > * 1bdadf46eff6804a ("locking/atomic: atomic64: support ARCH_ATOMIC") > > ... and it avoids any potential confusion with 'gen' meaning 'generated' or > similar. Sure! Thanks for giving the hint, I do agree it would look better and will rename in v2. > > Thanks, > Mark. > > > +{ > > + unsigned long mask = BIT_MASK(nr); > > + unsigned long *p = ((unsigned long *)addr) + BIT_WORD(nr); > > + > > + *p |= mask; > > +} [...] > > -- > > 2.36.1 Thanks, Al