From: Christoph Hellwig <hch@lst.de>
To: "Russell King (Oracle)" <linux@armlinux.org.uk>
Cc: Christoph Hellwig <hch@lst.de>, Will Deacon <will@kernel.org>,
linux-arch@vger.kernel.org, catalin.marinas@arm.com,
maz@kernel.org, mark.rutland@arm.com, robin.murphy@arm.com,
vgupta@kernel.org, arnd@arndb.de, bcain@quicinc.com,
geert@linux-m68k.org, monstr@monstr.eu, dinguyen@kernel.org,
shorne@gmail.com, mpe@ellerman.id.au, dalias@libc.org
Subject: Re: Cache maintenance for non-coherent DMA in arch_sync_dma_for_device()
Date: Wed, 8 Jun 2022 17:14:51 +0200 [thread overview]
Message-ID: <20220608151451.GA14424@lst.de> (raw)
In-Reply-To: <YqCPzTeKpCf3JZQw@shell.armlinux.org.uk>
On Wed, Jun 08, 2022 at 01:02:21PM +0100, Russell King (Oracle) wrote:
> Note that simply devolving the operations to this set is not optimal.
> If you notice, both my email and the table that was copied from my
> email makes two of the invalidate options dependent on the properties
> of the CPU cache architecture.
Yes, but that is nothing we can't do with a little optional arch
tunable. The whole point is that most architectures simply copy
and paste in the best case or get it wrong. So I'd have a nicely
working piece of generic code which is a win even if we still need
to override it in one or two places.
next prev parent reply other threads:[~2022-06-08 15:21 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-06-06 15:21 Cache maintenance for non-coherent DMA in arch_sync_dma_for_device() Will Deacon
2022-06-06 15:35 ` Russell King (Oracle)
2022-06-06 16:02 ` Robin Murphy
2022-06-06 16:16 ` Russell King (Oracle)
2022-06-08 8:49 ` Christoph Hellwig
2022-06-06 16:13 ` Catalin Marinas
2022-06-06 16:15 ` Ard Biesheuvel
2022-06-08 16:51 ` Catalin Marinas
2022-06-08 8:48 ` Christoph Hellwig
2022-06-08 12:02 ` Russell King (Oracle)
2022-06-08 15:14 ` Christoph Hellwig [this message]
2022-06-09 13:59 ` Will Deacon
2022-06-09 14:18 ` Christoph Hellwig
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