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Date:   Wed, 8 Jun 2022 17:14:51 +0200
From:   Christoph Hellwig <hch@lst.de>
To:     "Russell King (Oracle)" <linux@armlinux.org.uk>
Cc:     Christoph Hellwig <hch@lst.de>, Will Deacon <will@kernel.org>,
        linux-arch@vger.kernel.org, catalin.marinas@arm.com,
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Subject: Re: Cache maintenance for non-coherent DMA in
 arch_sync_dma_for_device()
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References: <20220606152150.GA31568@willie-the-truck> <20220608084841.GA17806@lst.de> <YqCPzTeKpCf3JZQw@shell.armlinux.org.uk>
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On Wed, Jun 08, 2022 at 01:02:21PM +0100, Russell King (Oracle) wrote:
> Note that simply devolving the operations to this set is not optimal.
> If you notice, both my email and the table that was copied from my
> email makes two of the invalidate options dependent on the properties
> of the CPU cache architecture.

Yes, but that is nothing we can't do with a little optional arch
tunable.  The whole point is that most architectures simply copy
and paste in the best case or get it wrong.  So I'd have a nicely
working piece of generic code which is a win even if we still need
to override it in one or two places.