From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id CFC83CCA485 for ; Tue, 28 Jun 2022 08:19:19 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S243774AbiF1ITS (ORCPT ); Tue, 28 Jun 2022 04:19:18 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:43604 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S243898AbiF1IS5 (ORCPT ); Tue, 28 Jun 2022 04:18:57 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 64A9A6370; Tue, 28 Jun 2022 01:17:29 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 0401A61231; Tue, 28 Jun 2022 08:17:29 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id DD2CFC341CD; Tue, 28 Jun 2022 08:17:25 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1656404248; bh=56vDPTinccyutph1yZKj95E6BJocnFoqUhaAVIL62sY=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=rCEAC2SBigqijBYp6OMMgxbh8KeqZedwJGPUR2YIkNilXQ8x+tBKFTFu/dOWr+kMk Xhq8Ws2xj/0/xP2QqoXjbxKwDb77EYzbKnbsjE/pbPvh40jjLrlkPqHI3MFJGyDlV+ XMfPNr0BF0vT76lkHYN6s+phQ95nHfr10FEf7cerv0ksBEhoWD7FDTS7AHz3DBthiP ijjAVggUMRpy/4a6UEuGWuVts9kikdkNj8NNUKqOTQpqU67h5JIy4futCp8RaZfnDg I3P4SMxDF+Ht0AKrEFoK/9a6MQQLd4tNRNR903q3XUgGoi2gJpTiZqPU/k9LNeL3oM kC1Zu91Wbs/wg== From: guoren@kernel.org To: palmer@rivosinc.com, arnd@arndb.de, mingo@redhat.com, will@kernel.org, longman@redhat.com, boqun.feng@gmail.com Cc: linux-riscv@lists.infradead.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, Guo Ren , Guo Ren , Peter Zijlstra Subject: [PATCH V7 2/5] asm-generic: ticket-lock: Use the same struct definitions with qspinlock Date: Tue, 28 Jun 2022 04:17:04 -0400 Message-Id: <20220628081707.1997728-3-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20220628081707.1997728-1-guoren@kernel.org> References: <20220628081707.1997728-1-guoren@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-arch@vger.kernel.org From: Guo Ren Let ticket_lock use the same struct definitions with qspinlock, and then we could move to combo spinlock (combine ticket & queue). Signed-off-by: Guo Ren Signed-off-by: Guo Ren Cc: Peter Zijlstra (Intel) Cc: Arnd Bergmann Cc: Palmer Dabbelt --- include/asm-generic/spinlock.h | 16 ++++++++-------- include/asm-generic/spinlock_types.h | 12 ++---------- 2 files changed, 10 insertions(+), 18 deletions(-) diff --git a/include/asm-generic/spinlock.h b/include/asm-generic/spinlock.h index f1e4fa100f5a..4caeb8cebe53 100644 --- a/include/asm-generic/spinlock.h +++ b/include/asm-generic/spinlock.h @@ -32,7 +32,7 @@ static __always_inline void arch_spin_lock(arch_spinlock_t *lock) { - u32 val = atomic_fetch_add(1<<16, lock); + u32 val = atomic_fetch_add(1<<16, &lock->val); u16 ticket = val >> 16; if (ticket == (u16)val) @@ -46,45 +46,45 @@ static __always_inline void arch_spin_lock(arch_spinlock_t *lock) * have no outstanding writes due to the atomic_fetch_add() the extra * orderings are free. */ - atomic_cond_read_acquire(lock, ticket == (u16)VAL); + atomic_cond_read_acquire(&lock->val, ticket == (u16)VAL); smp_mb(); } static __always_inline bool arch_spin_trylock(arch_spinlock_t *lock) { - u32 old = atomic_read(lock); + u32 old = atomic_read(&lock->val); if ((old >> 16) != (old & 0xffff)) return false; - return atomic_try_cmpxchg(lock, &old, old + (1<<16)); /* SC, for RCsc */ + return atomic_try_cmpxchg(&lock->val, &old, old + (1<<16)); /* SC, for RCsc */ } static __always_inline void arch_spin_unlock(arch_spinlock_t *lock) { u16 *ptr = (u16 *)lock + IS_ENABLED(CONFIG_CPU_BIG_ENDIAN); - u32 val = atomic_read(lock); + u32 val = atomic_read(&lock->val); smp_store_release(ptr, (u16)val + 1); } static __always_inline int arch_spin_is_locked(arch_spinlock_t *lock) { - u32 val = atomic_read(lock); + u32 val = atomic_read(&lock->val); return ((val >> 16) != (val & 0xffff)); } static __always_inline int arch_spin_is_contended(arch_spinlock_t *lock) { - u32 val = atomic_read(lock); + u32 val = atomic_read(&lock->val); return (s16)((val >> 16) - (val & 0xffff)) > 1; } static __always_inline int arch_spin_value_unlocked(arch_spinlock_t lock) { - u32 val = lock.counter; + u32 val = lock.val.counter; return ((val >> 16) == (val & 0xffff)); } diff --git a/include/asm-generic/spinlock_types.h b/include/asm-generic/spinlock_types.h index 8962bb730945..f534aa5de394 100644 --- a/include/asm-generic/spinlock_types.h +++ b/include/asm-generic/spinlock_types.h @@ -3,15 +3,7 @@ #ifndef __ASM_GENERIC_SPINLOCK_TYPES_H #define __ASM_GENERIC_SPINLOCK_TYPES_H -#include -typedef atomic_t arch_spinlock_t; - -/* - * qrwlock_types depends on arch_spinlock_t, so we must typedef that before the - * include. - */ -#include - -#define __ARCH_SPIN_LOCK_UNLOCKED ATOMIC_INIT(0) +#include +#include #endif /* __ASM_GENERIC_SPINLOCK_TYPES_H */ -- 2.36.1