From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id B937BC77B7D for ; Thu, 18 May 2023 13:13:27 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231594AbjERNN0 (ORCPT ); Thu, 18 May 2023 09:13:26 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:44938 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S231379AbjERNM6 (ORCPT ); Thu, 18 May 2023 09:12:58 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id 500A61FD8; Thu, 18 May 2023 06:12:33 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 53A0064F4E; Thu, 18 May 2023 13:12:22 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id 61FCFC433EF; Thu, 18 May 2023 13:12:07 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1684415541; bh=z5mkr//0fNawn45SMn5US81wCUZHNT6No8cwVZ30STk=; h=From:To:Cc:Subject:Date:In-Reply-To:References:From; b=dpq2AALe0mn8e3ICXMEMakWoQf7l4LZI9XJRL/KK8OthBuOAkkVBTJ2R5CWP7TUiJ Lijji9TT0GYg9fBUfTLk6wPK4WXm+jxmpEbBajfcmdzmeRiy0ygmmAsUBKmbllOfBm GnZ+bAVUV7Wyjr+nH981VRaTHsDByS7vGYmUPcEtDXWsZSvAZolKa4MH222LURagYw uPbNeSwfdDlP5bA43XtY6Onzy+BfMiZeJw1Yzm2DsAiO+M2GjYFej3rCH4OuDLXcD6 4jGrdnCY/T2Ybpkves9qxyv/jU92PgqrXB11ZASrYjazL2MnM291C7EyiNIopSXqXE IqaXJF5DKqkRA== From: guoren@kernel.org To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com, tglx@linutronix.de, peterz@infradead.org, luto@kernel.org, conor.dooley@microchip.com, heiko@sntech.de, jszhang@kernel.org, chenhuacai@kernel.org, apatel@ventanamicro.com, atishp@atishpatra.org, mark.rutland@arm.com, bjorn@kernel.org, paul.walmsley@sifive.com, catalin.marinas@arm.com, will@kernel.org, rppt@kernel.org, anup@brainfault.org, shihua@iscas.ac.cn, jiawei@iscas.ac.cn, liweiwei@iscas.ac.cn, luxufan@iscas.ac.cn, chunyu@iscas.ac.cn, tsu.yubo@gmail.com, wefu@redhat.com, wangjunqiang@iscas.ac.cn, kito.cheng@sifive.com, andy.chiu@sifive.com, vincent.chen@sifive.com, greentime.hu@sifive.com, corbet@lwn.net, wuwei2016@iscas.ac.cn, jrtc27@jrtc27.com Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org, Guo Ren Subject: [RFC PATCH 08/22] riscv: s64ilp32: Add asid support Date: Thu, 18 May 2023 09:09:59 -0400 Message-Id: <20230518131013.3366406-9-guoren@kernel.org> X-Mailer: git-send-email 2.36.1 In-Reply-To: <20230518131013.3366406-1-guoren@kernel.org> References: <20230518131013.3366406-1-guoren@kernel.org> MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Precedence: bulk List-ID: X-Mailing-List: linux-arch@vger.kernel.org From: Guo Ren The s32ilp32 uses 9 bits as asid_bits because of the xlen=32 limitation of CSR. The xlen of s64ilp32 is 64 bits in width, and the SATP CSR format is the same for Sv32, Sv39, Sv48, and Sv57. So this patch makes asid mechanism support s64ilp32 with maximum num_asids. Signed-off-by: Guo Ren Signed-off-by: Guo Ren --- arch/riscv/mm/context.c | 16 ++++++++++------ 1 file changed, 10 insertions(+), 6 deletions(-) diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c index 80ce9caba8d2..696a7ca41f55 100644 --- a/arch/riscv/mm/context.c +++ b/arch/riscv/mm/context.c @@ -20,9 +20,9 @@ DEFINE_STATIC_KEY_FALSE(use_asid_allocator); -static unsigned long asid_bits; +static xlen_t asid_bits; static unsigned long num_asids; -static unsigned long asid_mask; +static xlen_t asid_mask; static atomic_long_t current_version; @@ -225,14 +225,18 @@ static inline void set_mm(struct mm_struct *mm, unsigned int cpu) static int __init asids_init(void) { - unsigned long old; + xlen_t old; /* Figure-out number of ASID bits in HW */ old = csr_read(CSR_SATP); asid_bits = old | (SATP_ASID_MASK << SATP_ASID_SHIFT); csr_write(CSR_SATP, asid_bits); asid_bits = (csr_read(CSR_SATP) >> SATP_ASID_SHIFT) & SATP_ASID_MASK; - asid_bits = fls_long(asid_bits); +#if __riscv_xlen == 64 + asid_bits = fls64(asid_bits); +#else + asid_bits = fls(asid_bits); +#endif csr_write(CSR_SATP, old); /* @@ -265,9 +269,9 @@ static int __init asids_init(void) static_branch_enable(&use_asid_allocator); pr_info("ASID allocator using %lu bits (%lu entries)\n", - asid_bits, num_asids); + (ulong)asid_bits, num_asids); } else { - pr_info("ASID allocator disabled (%lu bits)\n", asid_bits); + pr_info("ASID allocator disabled (%lu bits)\n", (ulong)asid_bits); } return 0; -- 2.36.1