From: Andrew Jones <ajones@ventanamicro.com>
To: Alexandre Ghiti <alexghiti@rivosinc.com>
Cc: Will Deacon <will@kernel.org>,
"Aneesh Kumar K . V" <aneesh.kumar@linux.ibm.com>,
Andrew Morton <akpm@linux-foundation.org>,
Nick Piggin <npiggin@gmail.com>,
Peter Zijlstra <peterz@infradead.org>,
Mayuresh Chitale <mchitale@ventanamicro.com>,
Vincent Chen <vincent.chen@sifive.com>,
Paul Walmsley <paul.walmsley@sifive.com>,
Palmer Dabbelt <palmer@dabbelt.com>,
Albert Ou <aou@eecs.berkeley.edu>,
linux-arch@vger.kernel.org, linux-mm@kvack.org,
linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org
Subject: Re: [PATCH v2 3/4] riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb
Date: Fri, 28 Jul 2023 15:32:35 +0200 [thread overview]
Message-ID: <20230728-f2cd8ddd252c2ece2e438790@orel> (raw)
In-Reply-To: <20230727185553.980262-4-alexghiti@rivosinc.com>
On Thu, Jul 27, 2023 at 08:55:52PM +0200, Alexandre Ghiti wrote:
> Currently, when the range to flush covers more than one page (a 4K page or
> a hugepage), __flush_tlb_range() flushes the whole tlb. Flushing the whole
> tlb comes with a greater cost than flushing a single entry so we should
> flush single entries up to a certain threshold so that:
> threshold * cost of flushing a single entry < cost of flushing the whole
> tlb.
>
> This threshold is microarchitecture dependent and can/should be
> overwritten by vendors.
>
> Co-developed-by: Mayuresh Chitale <mchitale@ventanamicro.com>
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> ---
> arch/riscv/mm/tlbflush.c | 41 ++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 39 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
> index 3e4acef1f6bc..8017d2130e27 100644
> --- a/arch/riscv/mm/tlbflush.c
> +++ b/arch/riscv/mm/tlbflush.c
> @@ -24,13 +24,48 @@ static inline void local_flush_tlb_page_asid(unsigned long addr,
> : "memory");
> }
>
> +/*
> + * Flush entire TLB if number of entries to be flushed is greater
> + * than the threshold below. Platforms may override the threshold
> + * value based on marchid, mvendorid, and mimpid.
> + */
> +static unsigned long tlb_flush_all_threshold __read_mostly = 64;
> +
> +static void local_flush_tlb_range_threshold_asid(unsigned long start,
> + unsigned long size,
> + unsigned long stride,
> + unsigned long asid)
> +{
> + u16 nr_ptes_in_range = DIV_ROUND_UP(size, stride);
> + int i;
> +
> + if (nr_ptes_in_range > tlb_flush_all_threshold) {
> + if (asid != -1)
> + local_flush_tlb_all_asid(asid);
> + else
> + local_flush_tlb_all();
> + return;
> + }
> +
> + for (i = 0; i < nr_ptes_in_range; ++i) {
> + if (asid != -1)
> + local_flush_tlb_page_asid(start, asid);
> + else
> + local_flush_tlb_page(start);
> + start += stride;
> + }
> +}
> +
> static inline void local_flush_tlb_range(unsigned long start,
> unsigned long size, unsigned long stride)
> {
> if (size <= stride)
> local_flush_tlb_page(start);
> - else
> + else if (size == (unsigned long)-1)
The more we scatter this -1 around, especially now that we also need to
cast it, the more I think we should introduce a #define for it.
> local_flush_tlb_all();
> + else
> + local_flush_tlb_range_threshold_asid(start, size, stride, -1);
> +
> }
>
> static inline void local_flush_tlb_range_asid(unsigned long start,
> @@ -38,8 +73,10 @@ static inline void local_flush_tlb_range_asid(unsigned long start,
> {
> if (size <= stride)
> local_flush_tlb_page_asid(start, asid);
> - else
> + else if (size == (unsigned long)-1)
> local_flush_tlb_all_asid(asid);
> + else
> + local_flush_tlb_range_threshold_asid(start, size, stride, asid);
> }
>
> static void __ipi_flush_tlb_all(void *info)
> --
> 2.39.2
>
Otherwise,
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Thanks,
drew
next prev parent reply other threads:[~2023-07-28 13:34 UTC|newest]
Thread overview: 11+ messages / expand[flat|nested] mbox.gz Atom feed top
2023-07-27 18:55 [PATCH v2 0/4] riscv: tlb flush improvements Alexandre Ghiti
2023-07-27 18:55 ` [PATCH v2 1/4] riscv: Improve flush_tlb() Alexandre Ghiti
2023-07-28 13:35 ` Andrew Jones
2023-07-27 18:55 ` [PATCH v2 2/4] riscv: Improve flush_tlb_range() for hugetlb pages Alexandre Ghiti
2023-07-28 13:40 ` Andrew Jones
2023-07-27 18:55 ` [PATCH v2 3/4] riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb Alexandre Ghiti
2023-07-28 13:32 ` Andrew Jones [this message]
2023-07-28 13:51 ` Conor Dooley
2023-07-28 13:50 ` Conor Dooley
2023-07-27 18:55 ` [PATCH v2 4/4] riscv: Improve flush_tlb_kernel_range() Alexandre Ghiti
2023-07-28 13:48 ` Andrew Jones
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