* [PATCH v2 0/4] riscv: tlb flush improvements
@ 2023-07-27 18:55 Alexandre Ghiti
2023-07-27 18:55 ` [PATCH v2 1/4] riscv: Improve flush_tlb() Alexandre Ghiti
` (3 more replies)
0 siblings, 4 replies; 11+ messages in thread
From: Alexandre Ghiti @ 2023-07-27 18:55 UTC (permalink / raw)
To: Will Deacon, Aneesh Kumar K . V, Andrew Morton, Nick Piggin,
Peter Zijlstra, Mayuresh Chitale, Vincent Chen, Paul Walmsley,
Palmer Dabbelt, Albert Ou, linux-arch, linux-mm, linux-riscv,
linux-kernel
Cc: Alexandre Ghiti
This series optimizes the tlb flushes on riscv which used to simply
flush the whole tlb whatever the size of the range to flush or the size
of the stride.
Patch 3 introduces a threshold that is microarchitecture specific and
will very likely be modified by vendors, not sure though which mechanism
we'll use to do that (dt? alternatives? vendor initialization code?).
Next steps would be to implement:
- svinval extension as Mayuresh did here [1]
- BATCHED_UNMAP_TLB_FLUSH (I'll wait for arm64 patchset to land)
- MMU_GATHER_RCU_TABLE_FREE
- MMU_GATHER_MERGE_VMAS
Any other idea welcome.
[1] https://lore.kernel.org/linux-riscv/20230623123849.1425805-1-mchitale@ventanamicro.com/
Changes in v2:
- Make static tlb_flush_all_threshold, we'll figure out later how to
override this value on a vendor basis, as suggested by Conor and Palmer
- Fix nommu build, as reported by Conor
Alexandre Ghiti (4):
riscv: Improve flush_tlb()
riscv: Improve flush_tlb_range() for hugetlb pages
riscv: Make __flush_tlb_range() loop over pte instead of flushing the
whole tlb
riscv: Improve flush_tlb_kernel_range()
arch/riscv/include/asm/tlb.h | 8 ++-
arch/riscv/include/asm/tlbflush.h | 12 ++--
arch/riscv/mm/tlbflush.c | 93 +++++++++++++++++++++++++++----
3 files changed, 96 insertions(+), 17 deletions(-)
--
2.39.2
^ permalink raw reply [flat|nested] 11+ messages in thread
* [PATCH v2 1/4] riscv: Improve flush_tlb()
2023-07-27 18:55 [PATCH v2 0/4] riscv: tlb flush improvements Alexandre Ghiti
@ 2023-07-27 18:55 ` Alexandre Ghiti
2023-07-28 13:35 ` Andrew Jones
2023-07-27 18:55 ` [PATCH v2 2/4] riscv: Improve flush_tlb_range() for hugetlb pages Alexandre Ghiti
` (2 subsequent siblings)
3 siblings, 1 reply; 11+ messages in thread
From: Alexandre Ghiti @ 2023-07-27 18:55 UTC (permalink / raw)
To: Will Deacon, Aneesh Kumar K . V, Andrew Morton, Nick Piggin,
Peter Zijlstra, Mayuresh Chitale, Vincent Chen, Paul Walmsley,
Palmer Dabbelt, Albert Ou, linux-arch, linux-mm, linux-riscv,
linux-kernel
Cc: Alexandre Ghiti
For now, flush_tlb() simply calls flush_tlb_mm() which results in a
flush of the whole TLB. So let's use mmu_gather fields to provide a more
fine-grained flush of the TLB.
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
---
arch/riscv/include/asm/tlb.h | 8 +++++++-
arch/riscv/include/asm/tlbflush.h | 3 +++
arch/riscv/mm/tlbflush.c | 7 +++++++
3 files changed, 17 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/include/asm/tlb.h b/arch/riscv/include/asm/tlb.h
index 120bcf2ed8a8..1eb5682b2af6 100644
--- a/arch/riscv/include/asm/tlb.h
+++ b/arch/riscv/include/asm/tlb.h
@@ -15,7 +15,13 @@ static void tlb_flush(struct mmu_gather *tlb);
static inline void tlb_flush(struct mmu_gather *tlb)
{
- flush_tlb_mm(tlb->mm);
+#ifdef CONFIG_MMU
+ if (tlb->fullmm || tlb->need_flush_all)
+ flush_tlb_mm(tlb->mm);
+ else
+ flush_tlb_mm_range(tlb->mm, tlb->start, tlb->end,
+ tlb_get_unmap_size(tlb));
+#endif
}
#endif /* _ASM_RISCV_TLB_H */
diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h
index a09196f8de68..f5c4fb0ae642 100644
--- a/arch/riscv/include/asm/tlbflush.h
+++ b/arch/riscv/include/asm/tlbflush.h
@@ -32,6 +32,8 @@ static inline void local_flush_tlb_page(unsigned long addr)
#if defined(CONFIG_SMP) && defined(CONFIG_MMU)
void flush_tlb_all(void);
void flush_tlb_mm(struct mm_struct *mm);
+void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
+ unsigned long end, unsigned int page_size);
void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr);
void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
unsigned long end);
@@ -52,6 +54,7 @@ static inline void flush_tlb_range(struct vm_area_struct *vma,
}
#define flush_tlb_mm(mm) flush_tlb_all()
+#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all()
#endif /* !CONFIG_SMP || !CONFIG_MMU */
/* Flush a range of kernel pages */
diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
index 77be59aadc73..fa03289853d8 100644
--- a/arch/riscv/mm/tlbflush.c
+++ b/arch/riscv/mm/tlbflush.c
@@ -132,6 +132,13 @@ void flush_tlb_mm(struct mm_struct *mm)
__flush_tlb_range(mm, 0, -1, PAGE_SIZE);
}
+void flush_tlb_mm_range(struct mm_struct *mm,
+ unsigned long start, unsigned long end,
+ unsigned int page_size)
+{
+ __flush_tlb_range(mm, start, end - start, page_size);
+}
+
void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
{
__flush_tlb_range(vma->vm_mm, addr, PAGE_SIZE, PAGE_SIZE);
--
2.39.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 2/4] riscv: Improve flush_tlb_range() for hugetlb pages
2023-07-27 18:55 [PATCH v2 0/4] riscv: tlb flush improvements Alexandre Ghiti
2023-07-27 18:55 ` [PATCH v2 1/4] riscv: Improve flush_tlb() Alexandre Ghiti
@ 2023-07-27 18:55 ` Alexandre Ghiti
2023-07-28 13:40 ` Andrew Jones
2023-07-27 18:55 ` [PATCH v2 3/4] riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb Alexandre Ghiti
2023-07-27 18:55 ` [PATCH v2 4/4] riscv: Improve flush_tlb_kernel_range() Alexandre Ghiti
3 siblings, 1 reply; 11+ messages in thread
From: Alexandre Ghiti @ 2023-07-27 18:55 UTC (permalink / raw)
To: Will Deacon, Aneesh Kumar K . V, Andrew Morton, Nick Piggin,
Peter Zijlstra, Mayuresh Chitale, Vincent Chen, Paul Walmsley,
Palmer Dabbelt, Albert Ou, linux-arch, linux-mm, linux-riscv,
linux-kernel
Cc: Alexandre Ghiti
flush_tlb_range() uses a fixed stride of PAGE_SIZE and in its current form,
when a hugetlb mapping needs to be flushed, flush_tlb_range() flushes the
whole tlb: so set a stride of the size of the hugetlb mapping in order to
only flush the hugetlb mapping.
Note that THPs are directly handled by flush_pmd_tlb_range().
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
---
arch/riscv/mm/tlbflush.c | 10 +++++++++-
1 file changed, 9 insertions(+), 1 deletion(-)
diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
index fa03289853d8..3e4acef1f6bc 100644
--- a/arch/riscv/mm/tlbflush.c
+++ b/arch/riscv/mm/tlbflush.c
@@ -3,6 +3,7 @@
#include <linux/mm.h>
#include <linux/smp.h>
#include <linux/sched.h>
+#include <linux/hugetlb.h>
#include <asm/sbi.h>
#include <asm/mmu_context.h>
@@ -147,7 +148,14 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
unsigned long end)
{
- __flush_tlb_range(vma->vm_mm, start, end - start, PAGE_SIZE);
+ unsigned long stride_shift;
+
+ stride_shift = is_vm_hugetlb_page(vma) ?
+ huge_page_shift(hstate_vma(vma)) :
+ PAGE_SHIFT;
+
+ __flush_tlb_range(vma->vm_mm,
+ start, end - start, 1 << stride_shift);
}
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
--
2.39.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 3/4] riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb
2023-07-27 18:55 [PATCH v2 0/4] riscv: tlb flush improvements Alexandre Ghiti
2023-07-27 18:55 ` [PATCH v2 1/4] riscv: Improve flush_tlb() Alexandre Ghiti
2023-07-27 18:55 ` [PATCH v2 2/4] riscv: Improve flush_tlb_range() for hugetlb pages Alexandre Ghiti
@ 2023-07-27 18:55 ` Alexandre Ghiti
2023-07-28 13:32 ` Andrew Jones
2023-07-28 13:50 ` Conor Dooley
2023-07-27 18:55 ` [PATCH v2 4/4] riscv: Improve flush_tlb_kernel_range() Alexandre Ghiti
3 siblings, 2 replies; 11+ messages in thread
From: Alexandre Ghiti @ 2023-07-27 18:55 UTC (permalink / raw)
To: Will Deacon, Aneesh Kumar K . V, Andrew Morton, Nick Piggin,
Peter Zijlstra, Mayuresh Chitale, Vincent Chen, Paul Walmsley,
Palmer Dabbelt, Albert Ou, linux-arch, linux-mm, linux-riscv,
linux-kernel
Cc: Alexandre Ghiti
Currently, when the range to flush covers more than one page (a 4K page or
a hugepage), __flush_tlb_range() flushes the whole tlb. Flushing the whole
tlb comes with a greater cost than flushing a single entry so we should
flush single entries up to a certain threshold so that:
threshold * cost of flushing a single entry < cost of flushing the whole
tlb.
This threshold is microarchitecture dependent and can/should be
overwritten by vendors.
Co-developed-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
---
arch/riscv/mm/tlbflush.c | 41 ++++++++++++++++++++++++++++++++++++++--
1 file changed, 39 insertions(+), 2 deletions(-)
diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
index 3e4acef1f6bc..8017d2130e27 100644
--- a/arch/riscv/mm/tlbflush.c
+++ b/arch/riscv/mm/tlbflush.c
@@ -24,13 +24,48 @@ static inline void local_flush_tlb_page_asid(unsigned long addr,
: "memory");
}
+/*
+ * Flush entire TLB if number of entries to be flushed is greater
+ * than the threshold below. Platforms may override the threshold
+ * value based on marchid, mvendorid, and mimpid.
+ */
+static unsigned long tlb_flush_all_threshold __read_mostly = 64;
+
+static void local_flush_tlb_range_threshold_asid(unsigned long start,
+ unsigned long size,
+ unsigned long stride,
+ unsigned long asid)
+{
+ u16 nr_ptes_in_range = DIV_ROUND_UP(size, stride);
+ int i;
+
+ if (nr_ptes_in_range > tlb_flush_all_threshold) {
+ if (asid != -1)
+ local_flush_tlb_all_asid(asid);
+ else
+ local_flush_tlb_all();
+ return;
+ }
+
+ for (i = 0; i < nr_ptes_in_range; ++i) {
+ if (asid != -1)
+ local_flush_tlb_page_asid(start, asid);
+ else
+ local_flush_tlb_page(start);
+ start += stride;
+ }
+}
+
static inline void local_flush_tlb_range(unsigned long start,
unsigned long size, unsigned long stride)
{
if (size <= stride)
local_flush_tlb_page(start);
- else
+ else if (size == (unsigned long)-1)
local_flush_tlb_all();
+ else
+ local_flush_tlb_range_threshold_asid(start, size, stride, -1);
+
}
static inline void local_flush_tlb_range_asid(unsigned long start,
@@ -38,8 +73,10 @@ static inline void local_flush_tlb_range_asid(unsigned long start,
{
if (size <= stride)
local_flush_tlb_page_asid(start, asid);
- else
+ else if (size == (unsigned long)-1)
local_flush_tlb_all_asid(asid);
+ else
+ local_flush_tlb_range_threshold_asid(start, size, stride, asid);
}
static void __ipi_flush_tlb_all(void *info)
--
2.39.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* [PATCH v2 4/4] riscv: Improve flush_tlb_kernel_range()
2023-07-27 18:55 [PATCH v2 0/4] riscv: tlb flush improvements Alexandre Ghiti
` (2 preceding siblings ...)
2023-07-27 18:55 ` [PATCH v2 3/4] riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb Alexandre Ghiti
@ 2023-07-27 18:55 ` Alexandre Ghiti
2023-07-28 13:48 ` Andrew Jones
3 siblings, 1 reply; 11+ messages in thread
From: Alexandre Ghiti @ 2023-07-27 18:55 UTC (permalink / raw)
To: Will Deacon, Aneesh Kumar K . V, Andrew Morton, Nick Piggin,
Peter Zijlstra, Mayuresh Chitale, Vincent Chen, Paul Walmsley,
Palmer Dabbelt, Albert Ou, linux-arch, linux-mm, linux-riscv,
linux-kernel
Cc: Alexandre Ghiti
This function used to simply flush the whole tlb of all harts, be more
subtile and try to only flush the range.
The problem is that we can only use PAGE_SIZE as stride since we don't know
the size of the underlying mapping and then this function will be improved
only if the size of the region to flush is < threshold * PAGE_SIZE.
Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
---
arch/riscv/include/asm/tlbflush.h | 11 +++++-----
arch/riscv/mm/tlbflush.c | 35 +++++++++++++++++++++++--------
2 files changed, 32 insertions(+), 14 deletions(-)
diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h
index f5c4fb0ae642..7426fdcd8ec5 100644
--- a/arch/riscv/include/asm/tlbflush.h
+++ b/arch/riscv/include/asm/tlbflush.h
@@ -37,6 +37,7 @@ void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr);
void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
unsigned long end);
+void flush_tlb_kernel_range(unsigned long start, unsigned long end);
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
#define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
@@ -53,15 +54,15 @@ static inline void flush_tlb_range(struct vm_area_struct *vma,
local_flush_tlb_all();
}
-#define flush_tlb_mm(mm) flush_tlb_all()
-#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all()
-#endif /* !CONFIG_SMP || !CONFIG_MMU */
-
/* Flush a range of kernel pages */
static inline void flush_tlb_kernel_range(unsigned long start,
unsigned long end)
{
- flush_tlb_all();
+ local_flush_tlb_all();
}
+#define flush_tlb_mm(mm) flush_tlb_all()
+#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all()
+#endif /* !CONFIG_SMP || !CONFIG_MMU */
+
#endif /* _ASM_RISCV_TLBFLUSH_H */
diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
index 8017d2130e27..96aeacb269d5 100644
--- a/arch/riscv/mm/tlbflush.c
+++ b/arch/riscv/mm/tlbflush.c
@@ -117,18 +117,27 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start,
unsigned long size, unsigned long stride)
{
struct flush_tlb_range_data ftd;
- struct cpumask *cmask = mm_cpumask(mm);
- unsigned int cpuid;
+ struct cpumask *cmask, full_cmask;
bool broadcast;
- if (cpumask_empty(cmask))
- return;
+ if (mm) {
+ unsigned int cpuid;
+
+ cmask = mm_cpumask(mm);
+ if (cpumask_empty(cmask))
+ return;
+
+ cpuid = get_cpu();
+ /* check if the tlbflush needs to be sent to other CPUs */
+ broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids;
+ } else {
+ cpumask_setall(&full_cmask);
+ cmask = &full_cmask;
+ broadcast = true;
+ }
- cpuid = get_cpu();
- /* check if the tlbflush needs to be sent to other CPUs */
- broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids;
if (static_branch_unlikely(&use_asid_allocator)) {
- unsigned long asid = atomic_long_read(&mm->context.id) & asid_mask;
+ unsigned long asid = mm ? atomic_long_read(&mm->context.id) & asid_mask : 0;
if (broadcast) {
if (riscv_use_ipi_for_rfence()) {
@@ -162,7 +171,8 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start,
}
}
- put_cpu();
+ if (mm)
+ put_cpu();
}
void flush_tlb_mm(struct mm_struct *mm)
@@ -194,6 +204,13 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
__flush_tlb_range(vma->vm_mm,
start, end - start, 1 << stride_shift);
}
+
+void flush_tlb_kernel_range(unsigned long start,
+ unsigned long end)
+{
+ __flush_tlb_range(NULL, start, end, PAGE_SIZE);
+}
+
#ifdef CONFIG_TRANSPARENT_HUGEPAGE
void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
unsigned long end)
--
2.39.2
^ permalink raw reply related [flat|nested] 11+ messages in thread
* Re: [PATCH v2 3/4] riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb
2023-07-27 18:55 ` [PATCH v2 3/4] riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb Alexandre Ghiti
@ 2023-07-28 13:32 ` Andrew Jones
2023-07-28 13:51 ` Conor Dooley
2023-07-28 13:50 ` Conor Dooley
1 sibling, 1 reply; 11+ messages in thread
From: Andrew Jones @ 2023-07-28 13:32 UTC (permalink / raw)
To: Alexandre Ghiti
Cc: Will Deacon, Aneesh Kumar K . V, Andrew Morton, Nick Piggin,
Peter Zijlstra, Mayuresh Chitale, Vincent Chen, Paul Walmsley,
Palmer Dabbelt, Albert Ou, linux-arch, linux-mm, linux-riscv,
linux-kernel
On Thu, Jul 27, 2023 at 08:55:52PM +0200, Alexandre Ghiti wrote:
> Currently, when the range to flush covers more than one page (a 4K page or
> a hugepage), __flush_tlb_range() flushes the whole tlb. Flushing the whole
> tlb comes with a greater cost than flushing a single entry so we should
> flush single entries up to a certain threshold so that:
> threshold * cost of flushing a single entry < cost of flushing the whole
> tlb.
>
> This threshold is microarchitecture dependent and can/should be
> overwritten by vendors.
>
> Co-developed-by: Mayuresh Chitale <mchitale@ventanamicro.com>
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> ---
> arch/riscv/mm/tlbflush.c | 41 ++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 39 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
> index 3e4acef1f6bc..8017d2130e27 100644
> --- a/arch/riscv/mm/tlbflush.c
> +++ b/arch/riscv/mm/tlbflush.c
> @@ -24,13 +24,48 @@ static inline void local_flush_tlb_page_asid(unsigned long addr,
> : "memory");
> }
>
> +/*
> + * Flush entire TLB if number of entries to be flushed is greater
> + * than the threshold below. Platforms may override the threshold
> + * value based on marchid, mvendorid, and mimpid.
> + */
> +static unsigned long tlb_flush_all_threshold __read_mostly = 64;
> +
> +static void local_flush_tlb_range_threshold_asid(unsigned long start,
> + unsigned long size,
> + unsigned long stride,
> + unsigned long asid)
> +{
> + u16 nr_ptes_in_range = DIV_ROUND_UP(size, stride);
> + int i;
> +
> + if (nr_ptes_in_range > tlb_flush_all_threshold) {
> + if (asid != -1)
> + local_flush_tlb_all_asid(asid);
> + else
> + local_flush_tlb_all();
> + return;
> + }
> +
> + for (i = 0; i < nr_ptes_in_range; ++i) {
> + if (asid != -1)
> + local_flush_tlb_page_asid(start, asid);
> + else
> + local_flush_tlb_page(start);
> + start += stride;
> + }
> +}
> +
> static inline void local_flush_tlb_range(unsigned long start,
> unsigned long size, unsigned long stride)
> {
> if (size <= stride)
> local_flush_tlb_page(start);
> - else
> + else if (size == (unsigned long)-1)
The more we scatter this -1 around, especially now that we also need to
cast it, the more I think we should introduce a #define for it.
> local_flush_tlb_all();
> + else
> + local_flush_tlb_range_threshold_asid(start, size, stride, -1);
> +
> }
>
> static inline void local_flush_tlb_range_asid(unsigned long start,
> @@ -38,8 +73,10 @@ static inline void local_flush_tlb_range_asid(unsigned long start,
> {
> if (size <= stride)
> local_flush_tlb_page_asid(start, asid);
> - else
> + else if (size == (unsigned long)-1)
> local_flush_tlb_all_asid(asid);
> + else
> + local_flush_tlb_range_threshold_asid(start, size, stride, asid);
> }
>
> static void __ipi_flush_tlb_all(void *info)
> --
> 2.39.2
>
Otherwise,
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Thanks,
drew
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 1/4] riscv: Improve flush_tlb()
2023-07-27 18:55 ` [PATCH v2 1/4] riscv: Improve flush_tlb() Alexandre Ghiti
@ 2023-07-28 13:35 ` Andrew Jones
0 siblings, 0 replies; 11+ messages in thread
From: Andrew Jones @ 2023-07-28 13:35 UTC (permalink / raw)
To: Alexandre Ghiti
Cc: Will Deacon, Aneesh Kumar K . V, Andrew Morton, Nick Piggin,
Peter Zijlstra, Mayuresh Chitale, Vincent Chen, Paul Walmsley,
Palmer Dabbelt, Albert Ou, linux-arch, linux-mm, linux-riscv,
linux-kernel
On Thu, Jul 27, 2023 at 08:55:50PM +0200, Alexandre Ghiti wrote:
> For now, flush_tlb() simply calls flush_tlb_mm() which results in a
> flush of the whole TLB. So let's use mmu_gather fields to provide a more
> fine-grained flush of the TLB.
>
> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> ---
> arch/riscv/include/asm/tlb.h | 8 +++++++-
> arch/riscv/include/asm/tlbflush.h | 3 +++
> arch/riscv/mm/tlbflush.c | 7 +++++++
> 3 files changed, 17 insertions(+), 1 deletion(-)
>
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 2/4] riscv: Improve flush_tlb_range() for hugetlb pages
2023-07-27 18:55 ` [PATCH v2 2/4] riscv: Improve flush_tlb_range() for hugetlb pages Alexandre Ghiti
@ 2023-07-28 13:40 ` Andrew Jones
0 siblings, 0 replies; 11+ messages in thread
From: Andrew Jones @ 2023-07-28 13:40 UTC (permalink / raw)
To: Alexandre Ghiti
Cc: Will Deacon, Aneesh Kumar K . V, Andrew Morton, Nick Piggin,
Peter Zijlstra, Mayuresh Chitale, Vincent Chen, Paul Walmsley,
Palmer Dabbelt, Albert Ou, linux-arch, linux-mm, linux-riscv,
linux-kernel
On Thu, Jul 27, 2023 at 08:55:51PM +0200, Alexandre Ghiti wrote:
> flush_tlb_range() uses a fixed stride of PAGE_SIZE and in its current form,
> when a hugetlb mapping needs to be flushed, flush_tlb_range() flushes the
> whole tlb: so set a stride of the size of the hugetlb mapping in order to
> only flush the hugetlb mapping.
>
> Note that THPs are directly handled by flush_pmd_tlb_range().
>
> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> ---
> arch/riscv/mm/tlbflush.c | 10 +++++++++-
> 1 file changed, 9 insertions(+), 1 deletion(-)
>
> diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
> index fa03289853d8..3e4acef1f6bc 100644
> --- a/arch/riscv/mm/tlbflush.c
> +++ b/arch/riscv/mm/tlbflush.c
> @@ -3,6 +3,7 @@
> #include <linux/mm.h>
> #include <linux/smp.h>
> #include <linux/sched.h>
> +#include <linux/hugetlb.h>
> #include <asm/sbi.h>
> #include <asm/mmu_context.h>
>
> @@ -147,7 +148,14 @@ void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr)
> void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
> unsigned long end)
> {
> - __flush_tlb_range(vma->vm_mm, start, end - start, PAGE_SIZE);
> + unsigned long stride_shift;
> +
> + stride_shift = is_vm_hugetlb_page(vma) ?
> + huge_page_shift(hstate_vma(vma)) :
> + PAGE_SHIFT;
We want the size below instead of the shift, so we can just use
huge_page_size() and PAGE_SIZE here.
> +
> + __flush_tlb_range(vma->vm_mm,
> + start, end - start, 1 << stride_shift);
Shouldn't need to wrap this line.
> }
> #ifdef CONFIG_TRANSPARENT_HUGEPAGE
> void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
> --
> 2.39.2
>
Otherwise,
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Thanks,
drew
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 4/4] riscv: Improve flush_tlb_kernel_range()
2023-07-27 18:55 ` [PATCH v2 4/4] riscv: Improve flush_tlb_kernel_range() Alexandre Ghiti
@ 2023-07-28 13:48 ` Andrew Jones
0 siblings, 0 replies; 11+ messages in thread
From: Andrew Jones @ 2023-07-28 13:48 UTC (permalink / raw)
To: Alexandre Ghiti
Cc: Will Deacon, Aneesh Kumar K . V, Andrew Morton, Nick Piggin,
Peter Zijlstra, Mayuresh Chitale, Vincent Chen, Paul Walmsley,
Palmer Dabbelt, Albert Ou, linux-arch, linux-mm, linux-riscv,
linux-kernel
On Thu, Jul 27, 2023 at 08:55:53PM +0200, Alexandre Ghiti wrote:
> This function used to simply flush the whole tlb of all harts, be more
> subtile and try to only flush the range.
>
> The problem is that we can only use PAGE_SIZE as stride since we don't know
> the size of the underlying mapping and then this function will be improved
> only if the size of the region to flush is < threshold * PAGE_SIZE.
>
> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> ---
> arch/riscv/include/asm/tlbflush.h | 11 +++++-----
> arch/riscv/mm/tlbflush.c | 35 +++++++++++++++++++++++--------
> 2 files changed, 32 insertions(+), 14 deletions(-)
>
> diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h
> index f5c4fb0ae642..7426fdcd8ec5 100644
> --- a/arch/riscv/include/asm/tlbflush.h
> +++ b/arch/riscv/include/asm/tlbflush.h
> @@ -37,6 +37,7 @@ void flush_tlb_mm_range(struct mm_struct *mm, unsigned long start,
> void flush_tlb_page(struct vm_area_struct *vma, unsigned long addr);
> void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
> unsigned long end);
> +void flush_tlb_kernel_range(unsigned long start, unsigned long end);
> #ifdef CONFIG_TRANSPARENT_HUGEPAGE
> #define __HAVE_ARCH_FLUSH_PMD_TLB_RANGE
> void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
> @@ -53,15 +54,15 @@ static inline void flush_tlb_range(struct vm_area_struct *vma,
> local_flush_tlb_all();
> }
>
> -#define flush_tlb_mm(mm) flush_tlb_all()
> -#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all()
> -#endif /* !CONFIG_SMP || !CONFIG_MMU */
> -
> /* Flush a range of kernel pages */
> static inline void flush_tlb_kernel_range(unsigned long start,
> unsigned long end)
> {
> - flush_tlb_all();
> + local_flush_tlb_all();
> }
>
> +#define flush_tlb_mm(mm) flush_tlb_all()
> +#define flush_tlb_mm_range(mm, start, end, page_size) flush_tlb_all()
> +#endif /* !CONFIG_SMP || !CONFIG_MMU */
> +
> #endif /* _ASM_RISCV_TLBFLUSH_H */
> diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
> index 8017d2130e27..96aeacb269d5 100644
> --- a/arch/riscv/mm/tlbflush.c
> +++ b/arch/riscv/mm/tlbflush.c
> @@ -117,18 +117,27 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start,
> unsigned long size, unsigned long stride)
> {
> struct flush_tlb_range_data ftd;
> - struct cpumask *cmask = mm_cpumask(mm);
> - unsigned int cpuid;
> + struct cpumask *cmask, full_cmask;
> bool broadcast;
>
> - if (cpumask_empty(cmask))
> - return;
> + if (mm) {
> + unsigned int cpuid;
> +
> + cmask = mm_cpumask(mm);
> + if (cpumask_empty(cmask))
> + return;
> +
> + cpuid = get_cpu();
> + /* check if the tlbflush needs to be sent to other CPUs */
> + broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids;
> + } else {
> + cpumask_setall(&full_cmask);
> + cmask = &full_cmask;
> + broadcast = true;
> + }
>
> - cpuid = get_cpu();
> - /* check if the tlbflush needs to be sent to other CPUs */
> - broadcast = cpumask_any_but(cmask, cpuid) < nr_cpu_ids;
> if (static_branch_unlikely(&use_asid_allocator)) {
> - unsigned long asid = atomic_long_read(&mm->context.id) & asid_mask;
> + unsigned long asid = mm ? atomic_long_read(&mm->context.id) & asid_mask : 0;
>
> if (broadcast) {
> if (riscv_use_ipi_for_rfence()) {
> @@ -162,7 +171,8 @@ static void __flush_tlb_range(struct mm_struct *mm, unsigned long start,
> }
> }
>
> - put_cpu();
> + if (mm)
> + put_cpu();
> }
>
> void flush_tlb_mm(struct mm_struct *mm)
> @@ -194,6 +204,13 @@ void flush_tlb_range(struct vm_area_struct *vma, unsigned long start,
> __flush_tlb_range(vma->vm_mm,
> start, end - start, 1 << stride_shift);
> }
> +
> +void flush_tlb_kernel_range(unsigned long start,
> + unsigned long end)
No need to wrap this line.
> +{
> + __flush_tlb_range(NULL, start, end, PAGE_SIZE);
> +}
> +
> #ifdef CONFIG_TRANSPARENT_HUGEPAGE
> void flush_pmd_tlb_range(struct vm_area_struct *vma, unsigned long start,
> unsigned long end)
> --
> 2.39.2
>
Otherwise,
Reviewed-by: Andrew Jones <ajones@ventanamicro.com>
Thanks,
drew
^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 3/4] riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb
2023-07-27 18:55 ` [PATCH v2 3/4] riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb Alexandre Ghiti
2023-07-28 13:32 ` Andrew Jones
@ 2023-07-28 13:50 ` Conor Dooley
1 sibling, 0 replies; 11+ messages in thread
From: Conor Dooley @ 2023-07-28 13:50 UTC (permalink / raw)
To: Alexandre Ghiti
Cc: Will Deacon, Aneesh Kumar K . V, Andrew Morton, Nick Piggin,
Peter Zijlstra, Mayuresh Chitale, Vincent Chen, Paul Walmsley,
Palmer Dabbelt, Albert Ou, linux-arch, linux-mm, linux-riscv,
linux-kernel
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On Thu, Jul 27, 2023 at 08:55:52PM +0200, Alexandre Ghiti wrote:
> Currently, when the range to flush covers more than one page (a 4K page or
> a hugepage), __flush_tlb_range() flushes the whole tlb. Flushing the whole
> tlb comes with a greater cost than flushing a single entry so we should
> flush single entries up to a certain threshold so that:
> threshold * cost of flushing a single entry < cost of flushing the whole
> tlb.
>
> This threshold is microarchitecture dependent and can/should be
> overwritten by vendors.
Please remove the latter part of this, as there is no infrastructure for
this at present, nor likely in the immediate future.
> Co-developed-by: Mayuresh Chitale <mchitale@ventanamicro.com>
> Signed-off-by: Mayuresh Chitale <mchitale@ventanamicro.com>
> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> ---
> arch/riscv/mm/tlbflush.c | 41 ++++++++++++++++++++++++++++++++++++++--
> 1 file changed, 39 insertions(+), 2 deletions(-)
>
> diff --git a/arch/riscv/mm/tlbflush.c b/arch/riscv/mm/tlbflush.c
> index 3e4acef1f6bc..8017d2130e27 100644
> --- a/arch/riscv/mm/tlbflush.c
> +++ b/arch/riscv/mm/tlbflush.c
> @@ -24,13 +24,48 @@ static inline void local_flush_tlb_page_asid(unsigned long addr,
> : "memory");
> }
>
> +/*
> + * Flush entire TLB if number of entries to be flushed is greater
> + * than the threshold below.
> Platforms may override the threshold
> + * value based on marchid, mvendorid, and mimpid.
And this too, as there is no infrastructure for this the comment is
misleading. This kind of thing should only be added when there is
actually a mechanism for doing so.
I did say I would think about how to do this, but I have not come up
with something. I dislike using the marchid/mvendorid/mimpid stuff if we
can avoid it, as there's no control over what actually gets put in there,
especially if people are going to use the open souce cores.
Do we even, unless under extreme duress, want to allow setting custom
values here via firmware? Sounds like a recipe for 1200 different
alternatives or a big LUT...
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^ permalink raw reply [flat|nested] 11+ messages in thread
* Re: [PATCH v2 3/4] riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb
2023-07-28 13:32 ` Andrew Jones
@ 2023-07-28 13:51 ` Conor Dooley
0 siblings, 0 replies; 11+ messages in thread
From: Conor Dooley @ 2023-07-28 13:51 UTC (permalink / raw)
To: Andrew Jones
Cc: Alexandre Ghiti, Will Deacon, Aneesh Kumar K . V, Andrew Morton,
Nick Piggin, Peter Zijlstra, Mayuresh Chitale, Vincent Chen,
Paul Walmsley, Palmer Dabbelt, Albert Ou, linux-arch, linux-mm,
linux-riscv, linux-kernel
[-- Attachment #1: Type: text/plain, Size: 333 bytes --]
On Fri, Jul 28, 2023 at 03:32:35PM +0200, Andrew Jones wrote:
> On Thu, Jul 27, 2023 at 08:55:52PM +0200, Alexandre Ghiti wrote:
> > + else if (size == (unsigned long)-1)
>
> The more we scatter this -1 around, especially now that we also need to
> cast it, the more I think we should introduce a #define for it.
Please.
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^ permalink raw reply [flat|nested] 11+ messages in thread
end of thread, other threads:[~2023-07-28 13:52 UTC | newest]
Thread overview: 11+ messages (download: mbox.gz follow: Atom feed
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2023-07-27 18:55 [PATCH v2 0/4] riscv: tlb flush improvements Alexandre Ghiti
2023-07-27 18:55 ` [PATCH v2 1/4] riscv: Improve flush_tlb() Alexandre Ghiti
2023-07-28 13:35 ` Andrew Jones
2023-07-27 18:55 ` [PATCH v2 2/4] riscv: Improve flush_tlb_range() for hugetlb pages Alexandre Ghiti
2023-07-28 13:40 ` Andrew Jones
2023-07-27 18:55 ` [PATCH v2 3/4] riscv: Make __flush_tlb_range() loop over pte instead of flushing the whole tlb Alexandre Ghiti
2023-07-28 13:32 ` Andrew Jones
2023-07-28 13:51 ` Conor Dooley
2023-07-28 13:50 ` Conor Dooley
2023-07-27 18:55 ` [PATCH v2 4/4] riscv: Improve flush_tlb_kernel_range() Alexandre Ghiti
2023-07-28 13:48 ` Andrew Jones
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