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From: guoren@kernel.org
To: arnd@arndb.de, guoren@kernel.org, palmer@rivosinc.com,
	tglx@linutronix.de, conor.dooley@microchip.com, heiko@sntech.de,
	apatel@ventanamicro.com, atishp@atishpatra.org, bjorn@kernel.org,
	paul.walmsley@sifive.com, anup@brainfault.org,
	jiawei@iscas.ac.cn, liweiwei@iscas.ac.cn, wefu@redhat.com,
	U2FsdGVkX1@gmail.com, wangjunqiang@iscas.ac.cn,
	kito.cheng@sifive.com, andy.chiu@sifive.com,
	vincent.chen@sifive.com, greentime.hu@sifive.com,
	wuwei2016@iscas.ac.cn, jrtc27@jrtc27.com, luto@kernel.org,
	fweimer@redhat.com, catalin.marinas@arm.com, hjl.tools@gmail.com
Cc: linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org,
	linux-riscv@lists.infradead.org,
	Guo Ren <guoren@linux.alibaba.com>
Subject: [RFC PATCH V2 15/38] riscv: s64ilp32: Add asid support
Date: Sun, 12 Nov 2023 01:14:51 -0500	[thread overview]
Message-ID: <20231112061514.2306187-16-guoren@kernel.org> (raw)
In-Reply-To: <20231112061514.2306187-1-guoren@kernel.org>

From: Guo Ren <guoren@linux.alibaba.com>

The s32ilp32 uses 9 bits as asid_bits because of the xlen=32
limitation of CSR. The xlen of s64ilp32 is 64 bits in width, and
the SATP CSR format is the same for Sv32, Sv39, Sv48, and Sv57. So
this patch makes asid mechanism support s64ilp32 with maximum
num_asids.

Signed-off-by: Guo Ren <guoren@linux.alibaba.com>
Signed-off-by: Guo Ren <guoren@kernel.org>
---
 arch/riscv/include/asm/tlbflush.h |  2 +-
 arch/riscv/mm/context.c           | 16 ++++++++++------
 2 files changed, 11 insertions(+), 7 deletions(-)

diff --git a/arch/riscv/include/asm/tlbflush.h b/arch/riscv/include/asm/tlbflush.h
index a09196f8de68..6793c3f835a0 100644
--- a/arch/riscv/include/asm/tlbflush.h
+++ b/arch/riscv/include/asm/tlbflush.h
@@ -12,7 +12,7 @@
 #include <asm/errata_list.h>
 
 #ifdef CONFIG_MMU
-extern unsigned long asid_mask;
+extern xlen_t asid_mask;
 
 static inline void local_flush_tlb_all(void)
 {
diff --git a/arch/riscv/mm/context.c b/arch/riscv/mm/context.c
index 12e22e7330e7..9eab9aa87dc6 100644
--- a/arch/riscv/mm/context.c
+++ b/arch/riscv/mm/context.c
@@ -20,9 +20,9 @@
 
 DEFINE_STATIC_KEY_FALSE(use_asid_allocator);
 
-static unsigned long asid_bits;
+static xlen_t asid_bits;
 static unsigned long num_asids;
-unsigned long asid_mask;
+xlen_t asid_mask;
 
 static atomic_long_t current_version;
 
@@ -227,14 +227,18 @@ static inline void set_mm(struct mm_struct *prev,
 
 static int __init asids_init(void)
 {
-	unsigned long old;
+	xlen_t old;
 
 	/* Figure-out number of ASID bits in HW */
 	old = csr_read(CSR_SATP);
 	asid_bits = old | (SATP_ASID_MASK << SATP_ASID_SHIFT);
 	csr_write(CSR_SATP, asid_bits);
 	asid_bits = (csr_read(CSR_SATP) >> SATP_ASID_SHIFT)  & SATP_ASID_MASK;
-	asid_bits = fls_long(asid_bits);
+#if __riscv_xlen == 64
+	asid_bits = fls64(asid_bits);
+#else
+	asid_bits = fls(asid_bits);
+#endif
 	csr_write(CSR_SATP, old);
 
 	/*
@@ -267,9 +271,9 @@ static int __init asids_init(void)
 		static_branch_enable(&use_asid_allocator);
 
 		pr_info("ASID allocator using %lu bits (%lu entries)\n",
-			asid_bits, num_asids);
+			(ulong)asid_bits, num_asids);
 	} else {
-		pr_info("ASID allocator disabled (%lu bits)\n", asid_bits);
+		pr_info("ASID allocator disabled (%lu bits)\n", (ulong)asid_bits);
 	}
 
 	return 0;
-- 
2.36.1


  parent reply	other threads:[~2023-11-12  6:16 UTC|newest]

Thread overview: 42+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2023-11-12  6:14 [RFC PATCH V2 00/38] rv64ilp32: Running ILP32 on RV64 ISA guoren
2023-11-12  6:14 ` [RFC PATCH V2 01/38] riscv: u64ilp32: Unify vdso32 & compat_vdso into vdso/Makefile guoren
2023-11-12  6:14 ` [RFC PATCH V2 02/38] riscv: u64ilp32: Remove compat_vdso/ guoren
2023-11-12  6:14 ` [RFC PATCH V2 03/38] riscv: u64ilp32: Add time-related vDSO common flow for vdso32 guoren
2023-11-12  6:14 ` [RFC PATCH V2 04/38] riscv: u64ilp32: Introduce ILP32 vdso for UXL=64 guoren
2023-11-12  6:14 ` [RFC PATCH V2 05/38] riscv: u64ilp32: Adjust vDSO kernel flow for 64ilp32 abi guoren
2023-11-12  6:14 ` [RFC PATCH V2 06/38] riscv: u64ilp32: Add signal support for compat guoren
2023-11-12  6:14 ` [RFC PATCH V2 07/38] riscv: u64ilp32: Add ptrace interface support guoren
2023-11-12  6:14 ` [RFC PATCH V2 08/38] riscv: u64ilp32: Adjust vDSO alternative for 64ilp32 abi guoren
2023-11-12  6:14 ` [RFC PATCH V2 09/38] riscv: u64ilp32: Add xlen_t in user_regs_struct guoren
2023-11-12  6:14 ` [RFC PATCH V2 10/38] riscv: u64ilp32: Remove the restriction of UXL=32 guoren
2023-11-12  6:14 ` [RFC PATCH V2 11/38] riscv: u64ilp32: Enable user space runtime switch guoren
2023-11-12  6:14 ` [RFC PATCH V2 12/38] riscv: s64ilp32: Unify ULL & UL into UXL in csr guoren
2023-11-12  6:14 ` [RFC PATCH V2 13/38] riscv: s64ilp32: Introduce xlen_t for 64ILP32 kernel guoren
2023-11-12  6:14 ` [RFC PATCH V2 14/38] riscv: s64ilp32: Add sbi support guoren
2023-11-12  6:14 ` guoren [this message]
2023-11-12  6:14 ` [RFC PATCH V2 16/38] riscv: s64ilp32: Introduce PTR_L and PTR_S guoren
2023-11-12  6:14 ` [RFC PATCH V2 17/38] riscv: s64ilp32: Adjust TASK_SIZE for s64ilp32 kernel guoren
2023-11-12  6:14 ` [RFC PATCH V2 18/38] riscv: s64ilp32: Add ebpf jit support guoren
2023-11-12  6:14 ` [RFC PATCH V2 19/38] riscv: s64ilp32: Add ELF32 support guoren
2023-11-12  6:14 ` [RFC PATCH V2 20/38] riscv: s64ilp32: Add ARCH_RV64ILP32 Kconfig option guoren
2023-11-12  6:14 ` [RFC PATCH V2 21/38] riscv: s64ilp32: Add MMU_SV32 mode support guoren
2023-11-12  6:14 ` [RFC PATCH V2 22/38] riscv: s64ilp32: Add MMU_SV39 " guoren
2023-11-12  6:14 ` [RFC PATCH V2 23/38] riscv: s64ilp32: Enable native atomic64 guoren
2023-11-12  6:15 ` [RFC PATCH V2 24/38] riscv: s64ilp32: Add TImode (128 int) support guoren
2023-11-12  6:15 ` [RFC PATCH V2 25/38] riscv: s64ilp32: Implement cmpxchg_double guoren
2023-11-12  6:15 ` [RFC PATCH V2 26/38] riscv: s64ilp32: Disable KVM guoren
2023-11-12  6:15 ` [RFC PATCH V2 27/38] riscv: s64ilp32: Correct the rv64ilp32 stackframe layout guoren
2023-11-12  6:15 ` [RFC PATCH V2 28/38] riscv: s64ilp32: Temporary workaround solution to gcc problem guoren
2023-11-12  6:15 ` [RFC PATCH V2 29/38] riscv: s64ilp32: Introduce ARCH_HAS_64ILP32_KERNEL for syscall guoren
2023-11-12  6:15 ` [RFC PATCH V2 30/38] riscv: s64ilp32: Add u32ilp32 ptrace support guoren
2023-11-12  6:15 ` [RFC PATCH V2 31/38] riscv: s64ilp32: Add u32ilp32 signal support guoren
2023-11-12  6:15 ` [RFC PATCH V2 32/38] riscv: s64ilp32: Validate harts by architecture name guoren
2023-11-12  6:15 ` [RFC PATCH V2 33/38] riscv: s64ilp32: Add rv64ilp32_defconfig guoren
2023-11-12  6:15 ` [RFC PATCH V2 34/38] riscv: Cleanup rv32_defconfig guoren
2023-11-12  6:15 ` [RFC PATCH V2 35/38] clocksource: riscv: s64ilp32: Use __riscv_xlen instead of CONFIG_32BIT guoren
2023-11-12  6:15 ` [RFC PATCH V2 36/38] irqchip: " guoren
2023-11-12  6:15 ` [RFC PATCH V2 37/38] add tinylab defconfig guoren
2023-11-12  6:15 ` [RFC PATCH V2 38/38] 64ilp32 v.s. 64lp64 guoren
2023-11-13  4:13 ` [RFC PATCH V2 00/38] rv64ilp32: Running ILP32 on RV64 ISA Guo Ren
2023-11-13  4:22 ` Guo Ren
2023-12-03 15:31 ` Guo Ren

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