Re: [PATCH v5 02/13] riscv: Do not fail to build on byte/halfword operations with Zawrs

Andrew Jones
2024-08-21T14:11:36Z

On Sun, Aug 18, 2024 at 08:35:27AM GMT, Alexandre Ghiti wrote:
> riscv does not have lr instructions on byte and halfword but the
> qspinlock implementation actually uses such atomics provided by the
> Zabha extension, so those sizes are legitimate.
>
> Then instead of failing to build, just fallback to the !Zawrs path.
>
> Signed-off-by: Alexandre Ghiti <alexghiti@rivosinc.com>
> ---
> arch/riscv/include/asm/cmpxchg.h | 5 +++++
> 1 file changed, 5 insertions(+)
>
> diff --git a/arch/riscv/include/asm/cmpxchg.h b/arch/riscv/include/asm/cmpxchg.h
> index ebbce134917c..ac1d7df898ef 100644
> --- a/arch/riscv/include/asm/cmpxchg.h
> +++ b/arch/riscv/include/asm/cmpxchg.h
> @@ -245,6 +245,11 @@ static __always_inline void __cmpwait(volatile void *ptr,
> : : : : no_zawrs);
>
> switch (size) {
> + case 1:
> + fallthrough;
> + case 2:
> + /* RISC-V doesn't have lr instructions on byte and half-word. */
> + goto no_zawrs;
> case 4:
> asm volatile(
> " lr.w %0, %1\n"
> --
> 2.39.2
>