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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-43b919dfb54sm2097287f8f.31.2026.03.25.12.36.11 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 25 Mar 2026 12:36:11 -0700 (PDT) Date: Wed, 25 Mar 2026 19:36:08 +0000 From: David Laight To: Catalin Marinas Cc: Ankur Arora , Andrew Morton , linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-pm@vger.kernel.org, bpf@vger.kernel.org, arnd@arndb.de, will@kernel.org, peterz@infradead.org, mark.rutland@arm.com, harisokn@amazon.com, cl@gentwo.org, ast@kernel.org, rafael@kernel.org, daniel.lezcano@linaro.org, memxor@gmail.com, zhenglifeng1@huawei.com, xueshuai@linux.alibaba.com, rdunlap@infradead.org, joao.m.martins@oracle.com, boris.ostrovsky@oracle.com, konrad.wilk@oracle.com Subject: Re: [PATCH v10 00/12] barrier: Add smp_cond_load_{relaxed,acquire}_timeout() Message-ID: <20260325193608.10e9eca5@pumpkin> In-Reply-To: References: <20260316013651.3225328-1-ankur.a.arora@oracle.com> <20260315184925.b6f93386e918ca79614843e3@linux-foundation.org> <874imftol4.fsf@oracle.com> <20260316233712.7cbfac27@pumpkin> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) Precedence: bulk X-Mailing-List: linux-arch@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Wed, 25 Mar 2026 15:55:21 +0000 Catalin Marinas wrote: > On Mon, Mar 16, 2026 at 11:37:12PM +0000, David Laight wrote: ... > > For osq_lock(), while an IPI will wake it up, there is also a small timing > > window where the IPI can happen before the ldx and so not actually wake up it. > > This is true whenever 'expr' is non-trivial. > > Hmm, I thought this is fine because of the implicit SEVL on exception > return but the arm64 __cmpwait_relaxed() does a SEVL+WFE which clears > any prior event, it can wait in theory forever when the event stream is > disabled. Not forever, there will be a timer interrupt in the end. > Expanding smp_cond_load_relaxed() into asm, we have something like: > > LDR X0, [PTR] > condition check for VAL || need_resched() with branch out > SEVL > WFE > LDXR X1, [PTR] > EOR X1, X1, X0 > CBNZ out > WFE > out: > > If the condition is updated to become true (need_resched()) after the > condition check but before the first WFE while *PTR remains unchanged, > the IPI won't do anything. Maybe we should revert 1cfc63b5ae60 ("arm64: > cmpwait: Clear event register before arming exclusive monitor"). Not > great but probably better than reverting f5bfdc8e3947 ("locking/osq: Use > optimized spinning loop for arm64")). Could you change the order to: LDR X0, [PTR] SEVL WFE condition check for VAL || need_resched() with branch out LDXR X1, [PTR] EOR X1, X1, X0 CBNZ out WFE out: that closes the timing window for the interrupt provided the condition check doesn't change the event register. I must get back to the osq_lock code again. I'm happy with the code - the per-cpu data is down to two cpu numbers. (Apart from the acquire/release semantics in a few places.) But the comments have got out of hand. Writing succinct and accurate comments is hard - too verbose and they hide too much code. David