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client-ip=165.204.84.17; helo=satlexmb07.amd.com; pr=C Received: from satlexmb07.amd.com (165.204.84.17) by SA2PEPF0000150B.mail.protection.outlook.com (10.167.242.43) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.20.9846.18 via Frontend Transport; Thu, 30 Apr 2026 09:48:56 +0000 Received: from BLRKPRNAYAK.amd.com (10.180.168.240) by satlexmb07.amd.com (10.181.42.216) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.17; Thu, 30 Apr 2026 04:48:51 -0500 From: K Prateek Nayak To: Thomas Gleixner , Ingo Molnar , "Peter Zijlstra" , Sebastian Andrzej Siewior , Catalin Marinas , "Will Deacon" CC: Darren Hart , Davidlohr Bueso , =?UTF-8?q?Andr=C3=A9=20Almeida?= , , , , , , K Prateek Nayak , Jisheng Zhang Subject: [PATCH v4 3/8] arm64/runtime-const: Introduce runtime_const_mask_32() Date: Thu, 30 Apr 2026 09:47:25 +0000 Message-ID: <20260430094730.31624-4-kprateek.nayak@amd.com> X-Mailer: git-send-email 2.43.0 In-Reply-To: <20260430094730.31624-1-kprateek.nayak@amd.com> References: <20260430094730.31624-1-kprateek.nayak@amd.com> Precedence: bulk X-Mailing-List: linux-arch@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Transfer-Encoding: 8bit Content-Type: text/plain X-ClientProxiedBy: satlexmb08.amd.com (10.181.42.217) To satlexmb07.amd.com (10.181.42.216) X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SA2PEPF0000150B:EE_|BN7PPF9507C739C:EE_ X-MS-Office365-Filtering-Correlation-Id: 101cdfd2-5961-4fc3-c2dc-08dea69db283 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|376014|7416014|82310400026|22082099003|56012099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: XBgyZuWsSqI58QXFfRWZ+hMoDTARFqFCTvOo6OMD736CMBSKJ25eFNnswKn7zqp7WQsLCodc0ATRsZiu80Uu/zt7QRd3UG9KJwVuegp0LMjfik9hOQ82tdizEfjhhlnoBKQ881uIShmArslZLwhZLwfrkSvPY5IhCzhW7S6UaahtPXsSp3I5zx4VWF8hP/zGQyennUNKXvboacL8F8HyQnmyjvMn6BaTep3Lpe1etoq23vMJQn3kD5ROaWxTBTrMQPmieZ9EPsRtC0DgvTe881F3cpK78QpS6MV+99Qutkxolh9v9xs6uFfXI6Mh4oYESsi8AqdHaLVQhvcrV0CLhPCKrYvqmrhMuKbL8Q/dW+ipFqMXtQJXJZ1OZT0aNcnMceE55jyRRUfCHN58sv2HJr+MOGZ+6QyUU/D+5q05wZPFfrtxG4Pld5AqQm0gIBUP X-OriginatorOrg: amd.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 30 Apr 2026 09:48:56.7611 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 101cdfd2-5961-4fc3-c2dc-08dea69db283 X-MS-Exchange-CrossTenant-Id: 3dd8961f-e488-4e60-8e11-a82d994e183d X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=3dd8961f-e488-4e60-8e11-a82d994e183d;Ip=[165.204.84.17];Helo=[satlexmb07.amd.com] X-MS-Exchange-CrossTenant-AuthSource: SA2PEPF0000150B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: BN7PPF9507C739C Futex hash computation requires a mask operation with read-only after init data that will be converted to a runtime constant in the subsequent commit. Introduce runtime_const_mask_32 to further optimize the mask operation in the futex hash computation hot path. GCC generates a: movz w1, #lo16, lsl #0 // w1 = bits [15:0] movk w1, #hi16, lsl #16 // w1 = full 32-bit value and w0, w0, w1 // w0 = w0 & w1 pattern to tackle arbitrary 32-bit masks and the same was also suggested by Claude which is implemented here. The final (__ret & mask) operation is intentiaonally placed outside of asm block to allow compilers to further optimize it if possible. __runtime_fixup_ptr() already patches a "movz, + movk lsl #16" sequence which has been reused to patch the same sequence for __runtime_fixup_mask(). Assisted-by: Claude:claude-sonnet-4-5 Signed-off-by: K Prateek Nayak --- changelog v3..v4: o Reverted back to using __ret as the macro variable to prevent collision with local varaibles at callsite. (Sashiko) o Separated out the & operation to prevent any confusion with operator precedence id "val" is an expression. (Sashiko) --- arch/arm64/include/asm/runtime-const.h | 19 +++++++++++++++++++ 1 file changed, 19 insertions(+) diff --git a/arch/arm64/include/asm/runtime-const.h b/arch/arm64/include/asm/runtime-const.h index 838145bc289d2..1db4faac8c373 100644 --- a/arch/arm64/include/asm/runtime-const.h +++ b/arch/arm64/include/asm/runtime-const.h @@ -36,6 +36,18 @@ :"r" (0u+(val))); \ __ret; }) +#define runtime_const_mask_32(val, sym) ({ \ + unsigned long __ret; \ + asm_inline("1:\t" \ + "movz %w0, #0xcdef\n\t" \ + "movk %w0, #0x89ab, lsl #16\n\t" \ + ".pushsection runtime_mask_" #sym ",\"a\"\n\t" \ + ".long 1b - .\n\t" \ + ".popsection" \ + :"=r" (__ret)); \ + __ret &= val; /* Allow compiler to optimize & op. */ \ + __ret; }) + #define runtime_const_init(type, sym) do { \ extern s32 __start_runtime_##type##_##sym[]; \ extern s32 __stop_runtime_##type##_##sym[]; \ @@ -73,6 +85,13 @@ static inline void __runtime_fixup_shift(void *where, unsigned long val) aarch64_insn_patch_text_nosync(p, insn); } +static inline void __runtime_fixup_mask(void *where, unsigned long val) +{ + __le32 *p = where; + __runtime_fixup_16(p, val); + __runtime_fixup_16(p+1, val >> 16); +} + static inline void runtime_const_fixup(void (*fn)(void *, unsigned long), unsigned long val, s32 *start, s32 *end) { -- 2.34.1