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[82.69.66.36]) by smtp.gmail.com with ESMTPSA id ffacd0b85a97d-49597371cc4sm5861840f8f.36.2026.11.08.13.32.55 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 08 Nov 2026 13:32:56 -0800 (PST) Date: Sun, 8 Nov 2026 21:32:54 +0000 From: David Laight To: Yunhui Cui Cc: pjw@kernel.org, palmer@dabbelt.com, aou@eecs.berkeley.edu, alex@ghiti.fr, dennis@kernel.org, tj@kernel.org, cl@gentwo.org, ast@kernel.org, daniel@iogearbox.net, andrii@kernel.org, martin.lau@linux.dev, eddyz87@gmail.com, memxor@gmail.com, song@kernel.org, yonghong.song@linux.dev, jolsa@kernel.org, bjorn@kernel.org, pulehui@huawei.com, puranjay@kernel.org, thuth@redhat.com, ajones@ventanamicro.com, ben.dooks@codethink.co.uk, rkrcmar@ventanamicro.com, samuel.holland@sifive.com, zong.li@sifive.com, conor.dooley@microchip.com, tglx@kernel.org, debug@rivosinc.com, seanwascoding@gmail.com, andybnac@gmail.com, menglong8.dong@gmail.com, cyrilbur@tenstorrent.com, wangruikang@iscas.ac.cn, atishp@rivosinc.com, apatel@ventanamicro.com, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-mm@kvack.org, bpf@vger.kernel.org, arnd@arndb.de, nathan@kernel.org, nick.desaulniers+lkml@gmail.com, morbo@google.com, justinstitt@google.com, qingfang.deng@siflower.com.cn, linux-arch@vger.kernel.org, llvm@lists.linux.dev, dave@stgolabs.net, emil@etsalapatis.com, ihor.solodrai@linux.dev, broonie@kernel.org Subject: Re: [PATCH v9 1/3] riscv: implement this_cpu operations Message-ID: <20261108213254.67805ef0@pumpkin> In-Reply-To: <20261108110406.97495-2-cuiyunhui@bytedance.com> References: <20261108110406.97495-1-cuiyunhui@bytedance.com> <20261108110406.97495-2-cuiyunhui@bytedance.com> X-Mailer: Claws Mail 4.1.1 (GTK 3.24.38; arm-unknown-linux-gnueabihf) X-Mailing-List: linux-arch@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=US-ASCII Content-Transfer-Encoding: 7bit On Sun, 8 Nov 2026 19:04:04 +0800 Yunhui Cui wrote: > RISC-V has no asm/percpu.h, so this_cpu_*() read-modify-write > operations use generic implementations that disable local interrupts. > > Implement RISC-V-specific this_cpu operations with preemption disabled > to keep accesses on the current CPU. Have you looked at some of the schemes (I think arm64 has the latest, but also s390) that do most per-cpu ops without disabling preemption. In particular they save the pre-emption check when pre-emption is enabled. Basically the code tells the scheduler which register contains the per-cpu data so that it can be 'magically' flipped during a context switch. David