From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.redhat.com ([66.187.233.31]:25000 "EHLO mx1.redhat.com") by vger.kernel.org with ESMTP id S965138AbWH2Q5s (ORCPT ); Tue, 29 Aug 2006 12:57:48 -0400 From: David Howells In-Reply-To: References: <20060829162055.GA31159@linux-mips.org> <44F395DE.10804@yahoo.com.au> <1156750249.3034.155.camel@laptopd505.fenrus.org> <11861.1156845927@warthog.cambridge.redhat.com> <5878.1156868702@warthog.cambridge.redhat.com> Subject: Re: Why Semaphore Hardware-Dependent? Date: Tue, 29 Aug 2006 17:57:36 +0100 Message-ID: <21013.1156870656@warthog.cambridge.redhat.com> Sender: linux-arch-owner@vger.kernel.org To: Christoph Lameter Cc: David Howells , Ralf Baechle , Nick Piggin , Arjan van de Ven , Dong Feng , ak@suse.de, Paul Mackerras , linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org List-ID: Christoph Lameter wrote: > > Some of these have LL/SC or equivalent instead, but ARM5 and before, FRV, > > M68K before 68020 to name but a few. > > This is all pretty ancient hardware, right? And they are mostly single > processor so no need to worry about concurrency. Just disable interrupts. No, they're not all ancient h/w, and "just disabling interrupts" can be really expensive. > > And anything that implements CMPXCHG with spinlocks is a really bad > > candidate for CMPXCHG-based rwsems. > > Those will optimize out if it is a single processor configuration. Not necessarily. Consider preemption. David