From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.redhat.com ([66.187.233.31]:2226 "EHLO mx1.redhat.com") by vger.kernel.org with ESMTP id S1751183AbWDEJWM (ORCPT ); Wed, 5 Apr 2006 05:22:12 -0400 From: David Howells Subject: [PATCH] Improve data-dependency memory barrier example in documentation Date: Wed, 05 Apr 2006 10:22:03 +0100 Message-ID: <29899.1144228923@warthog.cambridge.redhat.com> Sender: linux-arch-owner@vger.kernel.org To: torvalds@osdl.org, akpm@osdl.org Cc: linux-kernel@vger.kernel.org, linux-arch@vger.kernel.org List-ID: In the memory barrier document, improve the example of the data dependency barrier situation by: (1) showing the initial values of the variables involved; and (2) repeating the instruction sequence description, this time with the data dependency barrier actually shown to make it clear what the revised sequence actually is. Signed-Off-By: David Howells --- warthog>diffstat -p1 /tmp/mb.diff Documentation/memory-barriers.txt | 16 +++++++++++++++- 1 file changed, 15 insertions(+), 1 deletion(-) diff --git a/Documentation/memory-barriers.txt b/Documentation/memory-barriers.txt index f855031..822fc45 100644 --- a/Documentation/memory-barriers.txt +++ b/Documentation/memory-barriers.txt @@ -610,6 +610,7 @@ loads. Consider the following sequence CPU 1 CPU 2 ======================= ======================= + { B = 7; X = 9; Y = 8; C = &Y } STORE A = 1 STORE B = 2 @@ -651,7 +652,20 @@ In the above example, CPU 2 perceives th (which would be B) coming after the the LOAD of C. If, however, a data dependency barrier were to be placed between the load of C -and the load of *C (ie: B) on CPU 2, then the following will occur: +and the load of *C (ie: B) on CPU 2: + + CPU 1 CPU 2 + ======================= ======================= + { B = 7; X = 9; Y = 8; C = &Y } + STORE A = 1 + STORE B = 2 + + STORE C = &B LOAD X + STORE D = 4 LOAD C (gets &B) + + LOAD *C (reads B) + +then the following will occur: +-------+ : : : : | | +------+ +-------+