From mboxrd@z Thu Jan 1 00:00:00 1970 From: Steven Price Subject: Re: [PATCH v6 02/26] arm64: mte: CPU feature detection and initial sysreg configuration Date: Mon, 13 Jul 2020 11:08:15 +0100 Message-ID: <2fb4b560-fb2f-7689-05f7-d908b55cd1eb@arm.com> References: <20200703153718.16973-1-catalin.marinas@arm.com> <20200703153718.16973-3-catalin.marinas@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8; format=flowed Content-Transfer-Encoding: 7bit Return-path: Received: from foss.arm.com ([217.140.110.172]:52068 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726523AbgGMKIW (ORCPT ); Mon, 13 Jul 2020 06:08:22 -0400 In-Reply-To: <20200703153718.16973-3-catalin.marinas@arm.com> Content-Language: en-GB Sender: linux-arch-owner@vger.kernel.org List-ID: To: Catalin Marinas , linux-arm-kernel@lists.infradead.org Cc: linux-arch@vger.kernel.org, Suzuki K Poulose , Szabolcs Nagy , Andrey Konovalov , Kevin Brodsky , Peter Collingbourne , linux-mm@kvack.org, Andrew Morton , Vincenzo Frascino , Will Deacon , Dave P Martin On 03/07/2020 16:36, Catalin Marinas wrote: > From: Vincenzo Frascino > > Add the cpufeature and hwcap entries to detect the presence of MTE on > the boot CPUs (primary and secondary). Any late secondary CPU not > supporting the feature, if detected during boot, will be parked. > > In addition, add the minimum SCTLR_EL1 and HCR_EL2 bits for enabling > MTE. Without subsequent setting of MAIR, these bits do not have an > effect on tag checking. > > Signed-off-by: Vincenzo Frascino > Co-developed-by: Catalin Marinas > Signed-off-by: Catalin Marinas > Cc: Will Deacon > Cc: Suzuki K Poulose This commit causes the feature bit to be exposed to a guest, but we don't at this point have any way of handling a guest which attempts to use MTE. This is 'fixed' by the first patch of my KVM MTE series[1], but perhaps the chunk modifying arch/arm64/kvm/sys_regs.c (see below) should be included here instead? That way we hide the feature until we're ready for a guest with MTE support. Steve [1] https://lore.kernel.org/r/20200713100102.53664-2-steven.price@arm.com ----8<---- diff --git a/arch/arm64/kvm/sys_regs.c b/arch/arm64/kvm/sys_regs.c index baf5ce9225ce..5ca974c93bd4 100644 --- a/arch/arm64/kvm/sys_regs.c +++ b/arch/arm64/kvm/sys_regs.c @@ -1104,6 +1104,8 @@ static u64 read_id_reg(const struct kvm_vcpu *vcpu, if (!vcpu_has_sve(vcpu)) val &= ~(0xfUL << ID_AA64PFR0_SVE_SHIFT); val &= ~(0xfUL << ID_AA64PFR0_AMU_SHIFT); + } else if (id == SYS_ID_AA64PFR1_EL1) { + val &= ~(0xfUL << ID_AA64PFR1_MTE_SHIFT); } else if (id == SYS_ID_AA64ISAR1_EL1 && !vcpu_has_ptrauth(vcpu)) { val &= ~((0xfUL << ID_AA64ISAR1_APA_SHIFT) | (0xfUL << ID_AA64ISAR1_API_SHIFT) |