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([2001:8003:e5b0:9f00:dbbc:1945:6e65:ec5]) by smtp.gmail.com with ESMTPSA id 20-20020a170902e9d400b001c567dcf22dsm2846570plk.281.2023.09.18.20.39.11 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits=128/128); Mon, 18 Sep 2023 20:39:16 -0700 (PDT) Message-ID: <31fa3aa7-c12c-3eb7-e9d2-5967a735ac78@redhat.com> Date: Tue, 19 Sep 2023 13:39:09 +1000 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:102.0) Gecko/20100101 Thunderbird/102.12.0 Subject: Re: [RFC PATCH v2 29/35] irqchip/gic-v3: Don't return errors from gic_acpi_match_gicc() Content-Language: en-US To: James Morse , linux-pm@vger.kernel.org, loongarch@lists.linux.dev, linux-acpi@vger.kernel.org, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-riscv@lists.infradead.org, kvmarm@lists.linux.dev Cc: x86@kernel.org, Salil Mehta , Russell King , Jean-Philippe Brucker , jianyong.wu@arm.com, justin.he@arm.com References: <20230913163823.7880-1-james.morse@arm.com> <20230913163823.7880-30-james.morse@arm.com> From: Gavin Shan In-Reply-To: <20230913163823.7880-30-james.morse@arm.com> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit Precedence: bulk List-ID: X-Mailing-List: linux-arch@vger.kernel.org On 9/14/23 02:38, James Morse wrote: > gic_acpi_match_gicc() is only called via gic_acpi_count_gicr_regions(). > It should only count the number of enabled redistributors, but it > also tries to sanity check the GICC entry, currently returning an > error if the Enabled bit is set, but the gicr_base_address is zero. > > Adding support for the online-capable bit to the sanity check > complicates it, for no benefit. The existing check implicitly > depends on gic_acpi_count_gicr_regions() previous failing to find > any GICR regions (as it is valid to have gicr_base_address of zero if > the redistributors are described via a GICR entry). > > Instead of complicating the check, remove it. Failures that happen > at this point cause the irqchip not to register, meaning no irqs > can be requested. The kernel grinds to a panic() pretty quickly. > > Without the check, MADT tables that exhibit this problem are still > caught by gic_populate_rdist(), which helpfully also prints what > went wrong: > | CPU4: mpidr 100 has no re-distributor! > > Signed-off-by: James Morse > --- > drivers/irqchip/irq-gic-v3.c | 18 ++++++------------ > 1 file changed, 6 insertions(+), 12 deletions(-) > With below nits resolved: Reviewed-by: Gavin Shan > diff --git a/drivers/irqchip/irq-gic-v3.c b/drivers/irqchip/irq-gic-v3.c > index 72d3cdebdad1..0f54811262eb 100644 > --- a/drivers/irqchip/irq-gic-v3.c > +++ b/drivers/irqchip/irq-gic-v3.c > @@ -2415,21 +2415,15 @@ static int __init gic_acpi_match_gicc(union acpi_subtable_headers *header, > > /* > * If GICC is enabled and has valid gicr base address, then it means > - * GICR base is presented via GICC > + * GICR base is presented via GICC. The redistributor is only known to > + * be accessible if the GICC is marked as enabled. If this bit is not > + * set, we'd need to add the redistributor at runtime, which isn't > + * supported. > */ > - if (acpi_gicc_is_usable(gicc) && gicc->gicr_base_address) { > + if (gicc->flags & ACPI_MADT_ENABLED && gicc->gicr_base_address) > acpi_data.enabled_rdists++; > - return 0; > - } > if (acpi_gicc_is_usable(gicc) && gicc->gicr_base_address) { > - /* > - * It's perfectly valid firmware can pass disabled GICC entry, driver > - * should not treat as errors, skip the entry instead of probe fail. > - */ > - if (!acpi_gicc_is_usable(gicc)) > - return 0; > - > - return -ENODEV; > + return 0; > } > > static int __init gic_acpi_count_gicr_regions(void) Thanks, Gavin