From: WANG Xuerui <kernel@xen0n.name>
To: Huacai Chen <chenhuacai@loongson.cn>,
Arnd Bergmann <arnd@arndb.de>, Andy Lutomirski <luto@kernel.org>,
Thomas Gleixner <tglx@linutronix.de>,
Peter Zijlstra <peterz@infradead.org>,
Andrew Morton <akpm@linux-foundation.org>,
David Airlie <airlied@linux.ie>, Jonathan Corbet <corbet@lwn.net>,
Linus Torvalds <torvalds@linux-foundation.org>
Cc: linux-arch@vger.kernel.org, linux-doc@vger.kernel.org,
linux-kernel@vger.kernel.org, Xuefeng Li <lixuefeng@loongson.cn>,
Yanteng Si <siyanteng@loongson.cn>,
Huacai Chen <chenhuacai@gmail.com>, Guo Ren <guoren@kernel.org>,
Xuerui Wang <kernel@xen0n.name>,
Jiaxun Yang <jiaxun.yang@flygoat.com>,
Stephen Rothwell <sfr@canb.auug.org.au>
Subject: Re: [PATCH V10 10/22] LoongArch: Add exception/interrupt handling
Date: Sun, 15 May 2022 17:07:04 +0800 [thread overview]
Message-ID: <3982e7e7-f98e-8d8b-f13b-2bfa10a69b95@xen0n.name> (raw)
In-Reply-To: <20220514080402.2650181-11-chenhuacai@loongson.cn>
Hi,
On 5/14/22 16:03, Huacai Chen wrote:
> Add the exception and interrupt handling machanism for basic LoongArch
> support.
>
> Signed-off-by: Huacai Chen <chenhuacai@loongson.cn>
> ---
> arch/loongarch/include/asm/branch.h | 21 +
> arch/loongarch/include/asm/bug.h | 23 +
> arch/loongarch/include/asm/entry-common.h | 13 +
> arch/loongarch/include/asm/hardirq.h | 24 +
> arch/loongarch/include/asm/hw_irq.h | 17 +
> arch/loongarch/include/asm/irq.h | 130 ++++
> arch/loongarch/include/asm/irq_regs.h | 27 +
> arch/loongarch/include/asm/irqflags.h | 78 +++
> arch/loongarch/include/asm/kdebug.h | 23 +
> arch/loongarch/include/asm/stackframe.h | 212 ++++++
> arch/loongarch/include/asm/stacktrace.h | 74 +++
> arch/loongarch/include/uapi/asm/break.h | 23 +
> arch/loongarch/kernel/access-helper.h | 13 +
> arch/loongarch/kernel/genex.S | 95 +++
> arch/loongarch/kernel/irq.c | 131 ++++
> arch/loongarch/kernel/traps.c | 755 ++++++++++++++++++++++
> 16 files changed, 1659 insertions(+)
> create mode 100644 arch/loongarch/include/asm/branch.h
> create mode 100644 arch/loongarch/include/asm/bug.h
> create mode 100644 arch/loongarch/include/asm/entry-common.h
> create mode 100644 arch/loongarch/include/asm/hardirq.h
> create mode 100644 arch/loongarch/include/asm/hw_irq.h
> create mode 100644 arch/loongarch/include/asm/irq.h
> create mode 100644 arch/loongarch/include/asm/irq_regs.h
> create mode 100644 arch/loongarch/include/asm/irqflags.h
> create mode 100644 arch/loongarch/include/asm/kdebug.h
> create mode 100644 arch/loongarch/include/asm/stackframe.h
> create mode 100644 arch/loongarch/include/asm/stacktrace.h
> create mode 100644 arch/loongarch/include/uapi/asm/break.h
> create mode 100644 arch/loongarch/kernel/access-helper.h
> create mode 100644 arch/loongarch/kernel/genex.S
> create mode 100644 arch/loongarch/kernel/irq.c
> create mode 100644 arch/loongarch/kernel/traps.c
This patch mostly looks good, except...
> (snip)
>
> +asmlinkage void cache_parity_error(void)
> +{
> + const int field = 2 * sizeof(unsigned long);
> + unsigned int reg_val;
> +
> + /* For the moment, report the problem and hang. */
> + pr_err("Cache error exception:\n");
> + pr_err("csr_merrera == %0*llx\n", field, csr_readq(LOONGARCH_CSR_MERRERA));
> + reg_val = csr_readl(LOONGARCH_CSR_MERRCTL);
> + pr_err("csr_merrctl == %08x\n", reg_val);
> +
> + pr_err("Decoded c0_cacheerr: %s cache fault in %s reference.\n",
> + reg_val & (1<<30) ? "secondary" : "primary",
> + reg_val & (1<<31) ? "data" : "insn");
> + if (((current_cpu_data.processor_id & 0xff0000) == PRID_COMP_LOONGSON)) {
> + pr_err("Error bits: %s%s%s%s%s%s%s%s\n",
> + reg_val & (1<<29) ? "ED " : "",
> + reg_val & (1<<28) ? "ET " : "",
> + reg_val & (1<<27) ? "ES " : "",
> + reg_val & (1<<26) ? "EE " : "",
> + reg_val & (1<<25) ? "EB " : "",
> + reg_val & (1<<24) ? "EI " : "",
> + reg_val & (1<<23) ? "E1 " : "",
> + reg_val & (1<<22) ? "E0 " : "");
> + } else {
> + pr_err("Error bits: %s%s%s%s%s%s%s\n",
> + reg_val & (1<<29) ? "ED " : "",
> + reg_val & (1<<28) ? "ET " : "",
> + reg_val & (1<<26) ? "EE " : "",
> + reg_val & (1<<25) ? "EB " : "",
> + reg_val & (1<<24) ? "EI " : "",
> + reg_val & (1<<23) ? "E1 " : "",
> + reg_val & (1<<22) ? "E0 " : "");
> + }
> + pr_err("IDX: 0x%08x\n", reg_val & ((1<<22)-1));
> +
> + panic("Can't handle the cache error!");
> +}
... this function. This implementation is completely wrong, as it's the
same logic on MIPS, but LoongArch's MERRCTL CSR is not arranged in the
same way. There are no individual error bits, for example.
You can simply replace this with a direct panic for now, for correctness.
With this fixed:
Reviewed-by: WANG Xuerui <git@xen0n.name>
next prev parent reply other threads:[~2022-05-15 9:07 UTC|newest]
Thread overview: 76+ messages / expand[flat|nested] mbox.gz Atom feed top
2022-05-14 8:03 [PATCH V10 00/22] arch: Add basic LoongArch support Huacai Chen
2022-05-14 8:03 ` [PATCH V10 01/22] Documentation: LoongArch: Add basic documentations Huacai Chen
2022-05-14 13:11 ` WANG Xuerui
2022-05-14 15:40 ` Huacai Chen
2022-05-15 12:41 ` Bagas Sanjaya
2022-05-15 13:14 ` Huacai Chen
2022-05-14 8:03 ` [PATCH V10 02/22] Documentation/zh_CN: Add basic LoongArch documentations Huacai Chen
2022-05-14 13:26 ` WANG Xuerui
2022-05-14 14:49 ` Huacai Chen
2022-05-14 8:03 ` [PATCH V3 03/22] LoongArch: Add elf-related definitions Huacai Chen
2022-05-14 13:29 ` WANG Xuerui
2022-05-14 14:11 ` Huacai Chen
2022-05-15 4:13 ` WANG Xuerui
2022-05-15 11:47 ` Huacai Chen
2022-05-14 8:03 ` [PATCH V10 04/22] LoongArch: Add writecombine support for drm Huacai Chen
2022-05-15 4:18 ` WANG Xuerui
2022-05-15 11:50 ` Huacai Chen
2022-05-14 8:03 ` [PATCH V10 05/22] LoongArch: Add build infrastructure Huacai Chen
2022-05-14 13:38 ` WANG Xuerui
2022-05-14 8:03 ` [PATCH V10 06/22] LoongArch: Add CPU definition headers Huacai Chen
2022-05-14 8:03 ` [PATCH V10 07/22] LoongArch: Add atomic/locking headers Huacai Chen
2022-05-14 8:03 ` [PATCH V10 08/22] LoongArch: Add other common headers Huacai Chen
2022-05-15 0:01 ` Jason A. Donenfeld
2022-05-15 11:42 ` Huacai Chen
2022-05-14 8:03 ` [PATCH V10 09/22] LoongArch: Add boot and setup routines Huacai Chen
2022-05-15 8:44 ` WANG Xuerui
2022-05-15 12:38 ` Huacai Chen
2022-05-16 2:41 ` WANG Xuerui
2022-05-14 8:03 ` [PATCH V10 10/22] LoongArch: Add exception/interrupt handling Huacai Chen
2022-05-15 9:07 ` WANG Xuerui [this message]
2022-05-15 13:00 ` Huacai Chen
2022-05-14 8:03 ` [PATCH V10 11/22] LoongArch: Add process management Huacai Chen
2022-05-15 9:20 ` WANG Xuerui
2022-05-15 13:25 ` Huacai Chen
2022-05-14 8:03 ` [PATCH V10 12/22] LoongArch: Add memory management Huacai Chen
2022-05-15 9:42 ` WANG Xuerui
2022-05-15 13:38 ` Huacai Chen
2022-05-14 8:03 ` [PATCH V10 13/22] LoongArch: Add system call support Huacai Chen
2022-05-14 13:53 ` WANG Xuerui
2022-05-14 14:39 ` Huacai Chen
2022-05-15 9:47 ` WANG Xuerui
2022-05-14 8:03 ` [PATCH V10 14/22] LoongArch: Add signal handling support Huacai Chen
2022-05-15 10:39 ` WANG Xuerui
2022-05-15 13:48 ` Huacai Chen
2022-05-16 3:51 ` WANG Xuerui
[not found] ` <87bkvxd12b.fsf@email.froward.int.ebiederm.org>
2022-05-16 15:02 ` WANG Xuerui
2022-05-17 2:08 ` Huacai Chen
2022-05-17 15:36 ` Eric W. Biederman
2022-05-14 8:03 ` [PATCH V10 15/22] LoongArch: Add ELF and module support Huacai Chen
2022-05-15 11:03 ` WANG Xuerui
2022-05-15 14:13 ` Huacai Chen
2022-05-14 8:03 ` [PATCH V10 16/22] LoongArch: Add misc common routines Huacai Chen
2022-05-14 12:56 ` Alexandre Belloni
2022-05-14 14:12 ` Huacai Chen
2022-05-14 16:00 ` Alexandre Belloni
2022-05-15 13:03 ` WANG Xuerui
2022-05-15 14:21 ` Huacai Chen
2022-05-14 8:03 ` [PATCH V10 17/22] LoongArch: Add some library functions Huacai Chen
2022-05-15 13:11 ` WANG Xuerui
2022-05-15 14:27 ` Huacai Chen
2022-05-14 8:03 ` [PATCH V10 18/22] LoongArch: Add PCI controller support Huacai Chen
2022-05-15 13:35 ` WANG Xuerui
2022-05-14 8:03 ` [PATCH V10 19/22] LoongArch: Add VDSO and VSYSCALL support Huacai Chen
2022-05-15 14:47 ` WANG Xuerui
2022-05-15 14:52 ` Huacai Chen
2022-05-14 8:04 ` [PATCH V10 20/22] LoongArch: Add multi-processor (SMP) support Huacai Chen
2022-05-15 14:16 ` WANG Xuerui
2022-05-15 14:47 ` Huacai Chen
2022-05-14 8:04 ` [PATCH V10 21/22] LoongArch: Add Non-Uniform Memory Access (NUMA) support Huacai Chen
2022-05-15 14:27 ` WANG Xuerui
2022-05-15 14:49 ` Huacai Chen
2022-05-14 8:04 ` [PATCH V10 22/22] LoongArch: Add Loongson-3 default config file Huacai Chen
2022-05-15 14:30 ` WANG Xuerui
2022-05-14 20:54 ` [PATCH V10 00/22] arch: Add basic LoongArch support Arnd Bergmann
2022-05-16 7:41 ` Huacai Chen
2022-05-15 15:09 ` WANG Xuerui
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