From mboxrd@z Thu Jan 1 00:00:00 1970 From: Arnd Bergmann Subject: Re: [PATCH v3 00/17] Cross-architecture definitions of relaxed MMIO accessors Date: Thu, 25 Sep 2014 17:15:14 +0200 Message-ID: <4240583.SJ4jiIW6Zy@wuerfel> References: <1411579056-16966-1-git-send-email-will.deacon@arm.com> <20140925145538.GN20043@arm.com> <3361270.4SkjDs5lox@wuerfel> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7Bit Return-path: Received: from mout.kundenserver.de ([212.227.126.131]:60712 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753028AbaIYPR5 (ORCPT ); Thu, 25 Sep 2014 11:17:57 -0400 In-Reply-To: <3361270.4SkjDs5lox@wuerfel> Sender: linux-arch-owner@vger.kernel.org List-ID: To: Will Deacon Cc: "linux-arch@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "benh@kernel.crashing.org" , "chris@zankel.net" , "cmetcalf@tilera.com" , "davem@davemloft.net" , "deller@gmx.de" , "dhowells@redhat.com" , "geert@linux-m68k.org" , "heiko.carstens@de.ibm.com" , "hpa@zytor.com" , "jcmvbkbc@gmail.com" , "jesper.nilsson@axis.com" , "mingo@redhat.com" , "monstr@monstr.eu" , "paulmck@linux.vnet.ibm.com" , "rdunlap@infradead.org" , "sam@ravnborg.org" , "schwidefsky@de.ibm.com" On Thursday 25 September 2014 17:07:47 Arnd Bergmann wrote: > The current version doesn't let you do that, so I'll keel the #ifdef > sections separate. This also means that I won't apply your patch 17: > we will keep needing the #ifdef to support all three relevant combinations: > > a) architectures that provide neither and want to get the defaults > from asm-generic > b) architectures that provide the non-relaxed versions and want tog > to get just the relaxed version from asm-generic > c) architectures that provide both > And here is the new version I applied: diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index 508a57257de5..3e976be3bdd4 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -174,6 +174,43 @@ static inline void writeq(u64 value, void __iomem *addr) #endif /* CONFIG_64BIT */ /* + * {read,write}{b,w,l,q}_relaxed() are like the regular version, but + * are not guaranteed to provide ordering against spinlocks or memory + * accesses. + */ +#ifndef readb_relaxed +#define readb_relaxed readb +#endif + +#ifndef readw_relaxed +#define readw_relaxed readw +#endif + +#ifndef readl_relaxed +#define readl_relaxed readl +#endif + +#ifndef readq_relaxed +#define readq_relaxed readq +#endif + +#ifndef writeb_relaxed +#define writeb_relaxed writeb +#endif + +#ifndef writew_relaxed +#define writew_relaxed writew +#endif + +#ifndef writel_relaxed +#define writel_relaxed writel +#endif + +#ifndef writeq_relaxed +#define writeq_relaxed writeq +#endif + +/* * {read,write}s{b,w,l,q}() repeatedly access the same memory address in * native endianness in 8-, 16-, 32- or 64-bit chunks (@count times). */ From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mout.kundenserver.de ([212.227.126.131]:60712 "EHLO mout.kundenserver.de" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1753028AbaIYPR5 (ORCPT ); Thu, 25 Sep 2014 11:17:57 -0400 From: Arnd Bergmann Subject: Re: [PATCH v3 00/17] Cross-architecture definitions of relaxed MMIO accessors Date: Thu, 25 Sep 2014 17:15:14 +0200 Message-ID: <4240583.SJ4jiIW6Zy@wuerfel> In-Reply-To: <3361270.4SkjDs5lox@wuerfel> References: <1411579056-16966-1-git-send-email-will.deacon@arm.com> <20140925145538.GN20043@arm.com> <3361270.4SkjDs5lox@wuerfel> MIME-Version: 1.0 Content-Transfer-Encoding: 7Bit Content-Type: text/plain; charset="us-ascii" Sender: linux-arch-owner@vger.kernel.org List-ID: To: Will Deacon Cc: "linux-arch@vger.kernel.org" , "linux-kernel@vger.kernel.org" , "benh@kernel.crashing.org" , "chris@zankel.net" , "cmetcalf@tilera.com" , "davem@davemloft.net" , "deller@gmx.de" , "dhowells@redhat.com" , "geert@linux-m68k.org" , "heiko.carstens@de.ibm.com" , "hpa@zytor.com" , "jcmvbkbc@gmail.com" , "jesper.nilsson@axis.com" , "mingo@redhat.com" , "monstr@monstr.eu" , "paulmck@linux.vnet.ibm.com" , "rdunlap@infradead.org" , "sam@ravnborg.org" , "schwidefsky@de.ibm.com" , "starvik@axis.com" , "takata@linux-m32r.org" , "tglx@linutronix.de" , "tony.luck@intel.com" , "daniel.thompson@linaro.org" , "broonie@linaro.org" , "linux@arm.linux.org.uk" , "thierry.reding@gmail.com" Message-ID: <20140925151514.b7_0MbOAe98EuzWXY8cH2SAYpUdP-QuLpZ-aqK4rLlA@z> On Thursday 25 September 2014 17:07:47 Arnd Bergmann wrote: > The current version doesn't let you do that, so I'll keel the #ifdef > sections separate. This also means that I won't apply your patch 17: > we will keep needing the #ifdef to support all three relevant combinations: > > a) architectures that provide neither and want to get the defaults > from asm-generic > b) architectures that provide the non-relaxed versions and want tog > to get just the relaxed version from asm-generic > c) architectures that provide both > And here is the new version I applied: diff --git a/include/asm-generic/io.h b/include/asm-generic/io.h index 508a57257de5..3e976be3bdd4 100644 --- a/include/asm-generic/io.h +++ b/include/asm-generic/io.h @@ -174,6 +174,43 @@ static inline void writeq(u64 value, void __iomem *addr) #endif /* CONFIG_64BIT */ /* + * {read,write}{b,w,l,q}_relaxed() are like the regular version, but + * are not guaranteed to provide ordering against spinlocks or memory + * accesses. + */ +#ifndef readb_relaxed +#define readb_relaxed readb +#endif + +#ifndef readw_relaxed +#define readw_relaxed readw +#endif + +#ifndef readl_relaxed +#define readl_relaxed readl +#endif + +#ifndef readq_relaxed +#define readq_relaxed readq +#endif + +#ifndef writeb_relaxed +#define writeb_relaxed writeb +#endif + +#ifndef writew_relaxed +#define writew_relaxed writew +#endif + +#ifndef writel_relaxed +#define writel_relaxed writel +#endif + +#ifndef writeq_relaxed +#define writeq_relaxed writeq +#endif + +/* * {read,write}s{b,w,l,q}() repeatedly access the same memory address in * native endianness in 8-, 16-, 32- or 64-bit chunks (@count times). */