[Fwd: [PATCH 2.6.13] lockless pagecache 2/7]

[Fwd: [PATCH 2.6.13] lockless pagecache 2/7]

[Nick Piggin]

[-- Attachment #1: Type: text/plain, Size: 603 bytes --]

Forwarded to linux-arch for comments.

It would be preferable if replies could go to the lkml
thread, but either way is fine.

Thanks,
Nick

-------- Original Message --------
Subject: [PATCH 2.6.13] lockless pagecache 2/7
Date: Fri, 02 Sep 2005 16:29:10 +1000
From: Nick Piggin <nickpiggin@yahoo.com.au>
To: Linux Memory Management <linux-mm@kvack.org>,	linux-kernel <linux-kernel@vger.kernel.org>
References: <4317F071.1070403@yahoo.com.au> <4317F0F9.1080602@yahoo.com.au>

2/7
Implement atomic_cmpxchg for i386 and ppc64. Is there any
architecture that won't be able to implement such an operation?


[-- Attachment #2: atomic_cmpxchg.patch --]
[-- Type: text/plain, Size: 1102 bytes --]

Introduce an atomic_cmpxchg operation. Implement this for i386 and ppc64.

Signed-off-by: Nick Piggin <npiggin@suse.de>

Index: linux-2.6/include/asm-i386/atomic.h
===================================================================
--- linux-2.6.orig/include/asm-i386/atomic.h
+++ linux-2.6/include/asm-i386/atomic.h
@@ -215,6 +215,8 @@ static __inline__ int atomic_sub_return(
 	return atomic_add_return(-i,v);
 }
 
+#define atomic_cmpxchg(v, old, new)	((int)cmpxchg(&((v)->counter), old, new))
+
 #define atomic_inc_return(v)  (atomic_add_return(1,v))
 #define atomic_dec_return(v)  (atomic_sub_return(1,v))
 
Index: linux-2.6/include/asm-ppc64/atomic.h
===================================================================
--- linux-2.6.orig/include/asm-ppc64/atomic.h
+++ linux-2.6/include/asm-ppc64/atomic.h
@@ -162,6 +162,8 @@ static __inline__ int atomic_dec_return(
 	return t;
 }
 
+#define atomic_cmpxchg(v, o, n)	((int)cmpxchg(&((v)->counter), (o), (n)))
+
 #define atomic_sub_and_test(a, v)	(atomic_sub_return((a), (v)) == 0)
 #define atomic_dec_and_test(v)		(atomic_dec_return((v)) == 0)
 

Re: [Fwd: [PATCH 2.6.13] lockless pagecache 2/7]

[David S. Miller]

Sparc32 lacks compare and exchange.  I think PARISC lacks it
as well.

For these older SMP systems, at best you can assume there
is some kind of spinlock and perhaps a straight atomic
exchange instruction.  You really can't assume the existance
of compare-and-swap.

Re: [Fwd: [PATCH 2.6.13] lockless pagecache 2/7]

[Nick Piggin]

David S. Miller wrote:
> Sparc32 lacks compare and exchange.  I think PARISC lacks it
> as well.
> 
> For these older SMP systems, at best you can assume there
> is some kind of spinlock and perhaps a straight atomic
> exchange instruction.  You really can't assume the existance
> of compare-and-swap.
> 

Thanks David, I suspected as much.

PARISC emulates cmpxchg. I suspect sparc could do the same?
(provided all access goes through the atomic_xxx accessors)

Nick

-- 
SUSE Labs, Novell Inc.

Send instant messages to your online friends http://au.messenger.yahoo.com 

Re: [Fwd: [PATCH 2.6.13] lockless pagecache 2/7]

[Matthew Wilcox]

On Fri, Sep 02, 2005 at 06:05:49PM +1000, Nick Piggin wrote:
> David S. Miller wrote:
> >Sparc32 lacks compare and exchange.  I think PARISC lacks it
> >as well.
> >
> >For these older SMP systems, at best you can assume there
> >is some kind of spinlock and perhaps a straight atomic
> >exchange instruction.  You really can't assume the existance
> >of compare-and-swap.
> >
> 
> Thanks David, I suspected as much.
> 
> PARISC emulates cmpxchg. I suspect sparc could do the same?
> (provided all access goes through the atomic_xxx accessors)

If Sparc has atomic stores to aligned addresses (and I bet it does),
then the PA-RISC style emulation should work just fine.