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Tue, 14 Jan 2025 02:02:05 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: linux-arch@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Tue, 14 Jan 2025 08:01:22 +0100 From: "Arnd Bergmann" To: "Jiaxun Yang" , =?UTF-8?Q?Mateusz_Jo=C5=84czyk?= , "linux-mips@vger.kernel.org" , Linux-Arch , linux-kernel@vger.kernel.org Cc: "Baoquan He" , "Thomas Bogendoerfer" , "Alexandre Belloni" , regressions@lists.linux.dev Message-Id: <436dc4cb-6d99-415e-b20c-52f3221f85fc@app.fastmail.com> In-Reply-To: <99f75c66-4c2d-45dc-a808-b5ba440c7551@app.fastmail.com> References: <90b5b76d-25b6-4cdc-91ed-07ac930dc519@o2.pl> <99f75c66-4c2d-45dc-a808-b5ba440c7551@app.fastmail.com> Subject: Re: [REGRESSION] mipsel: no RTC CMOS on the Malta platform in QEMU Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable On Tue, Jan 14, 2025, at 00:29, Jiaxun Yang wrote: > =E5=9C=A82025=E5=B9=B41=E6=9C=8813=E6=97=A5=E4=B8=80=E6=9C=88 =E4=B8=8B= =E5=8D=8810:16=EF=BC=8CMateusz Jo=C5=84czyk=E5=86=99=E9=81=93=EF=BC=9A >> The mediator seems to be that this bad commit causes=20 >> arch/mips/include/asm/io.h >> to #include at the end. As a side effect, this cau= ses >> the PCI_IOBASE macro to be defined: >> >> #ifndef PCI_IOBASE >> #define PCI_IOBASE ((void __iomem *)0) >> #endif >> >> That PCI_IOBASE value above is AFAIK incorrect for MIPS (it should be >> defined to mips_io_port_base as far as I can tell), but this does not=20 >> matter much here. > > You are right, this is what should be done. > > A quick fix would be #undef PCI_IOBASE in arch/mips/include/asm/io.h > just after including #include , with ralink and loon= gson64 > as exception. > > In the long term, we should scrutinize platform usage of mips_io_base > following ralink's approach. I think we are close to the point of being able to remove the broken default PCI_IOBASE: the NULL pointer here is almost always wrong, and mainly existed to shut up build failures on architectures that have no port I/O at all. I know that sparc32 and m68k have cases that actually rely on the broken PCI_IOBASE, so those need a local workaround, not sure if some mips platform also falls into this category, as I have not looked here in detail. Hopefully we can get to a point where any reference to port I/O (inb/outb, PCI_IOPORT, mips_io_port_base, ...) is guarded by an #ifdef CONFIG_HAS_IOPORT check, and this is set exactly on those platforms that set mips_io_port_base to a valid address. Arnd