[PATCH 0/7][RFC] Move Marvell MBUS window handling into drivers

[PATCH 0/7][RFC] Move Marvell MBUS window handling into drivers

[Lennert Buytenhek]

Hi all,

Various Marvell chips (ARM SoCs, MIPS/PPC northbridges,
standalone PCI/PCIe SATA/etc. controllers) use an on-chip bus
called MBUS.

An MBUS bus address consists of not only a 32/64-bit address, but
also of a target/attribute ID, which identify which of the connected
MBUS peripherals the access is intended for.  I.e., transactions are
routed explicitly, rather than implicitly based on their address.

Peripherals map DMA addresses (as handed to them via e.g. TX/RX
descriptors) to MBUS bus addresses via a set of programmable
per-peripheral address map windows.

In the typical ARM/PPC case, each DMA-capable MBUS peripheral is
programmed such that its entire DMA address range points to the
on-chip DRAM controller.  (But if you wanted, you could also map a
peripheral's entire DMA address range to e.g. the PCI MEM address
range of some on-chip PCI/PCIe controller.)

For things like PCIe SATA controllers, you don't need to worry
about setting these address windows, but on most of the ARM/PPC/MIPS
stuff, the mapping windows don't contain valid values after reset,
and the programming has to be done by the bootloader or the kernel.

While the MBUS address map registers are an integral part of each
peripheral's own register set, these MBUS address map windows are
currently programmed directly by platform code, leading to such
gems as arch/arm/mach-orion/addr-map.c and
arch/powerpc/platforms/chrp/pegasos_eth.c.

This patch set is an initial attempt at moving programming of the
MBUS register windows for the set of MBUS peripherals that we currently
have in-tree drivers for from platform code into drivers.

With these patches, info about DRAM target/attribute IDs is prepared
by the platform code as usual, but then passed into platform drivers
via platform device data, instead of programming that data into the
peripherals directly.

This avoids duplicating the window programming code across each
platform that wants to use these peripherals, and avoids exposing
internal peripheral register set details outside of their drivers.

Comments appreciated.


thanks,
Lennert
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[PATCH 0/7][RFC] Move Marvell MBUS window handling into drivers

[Lennert Buytenhek]

Hi all,

Various Marvell chips (ARM SoCs, MIPS/PPC northbridges,
standalone PCI/PCIe SATA/etc. controllers) use an on-chip bus
called MBUS.

An MBUS bus address consists of not only a 32/64-bit address, but
also of a target/attribute ID, which identify which of the connected
MBUS peripherals the access is intended for.  I.e., transactions are
routed explicitly, rather than implicitly based on their address.

Peripherals map DMA addresses (as handed to them via e.g. TX/RX
descriptors) to MBUS bus addresses via a set of programmable
per-peripheral address map windows.

In the typical ARM/PPC case, each DMA-capable MBUS peripheral is
programmed such that its entire DMA address range points to the
on-chip DRAM controller.  (But if you wanted, you could also map a
peripheral's entire DMA address range to e.g. the PCI MEM address
range of some on-chip PCI/PCIe controller.)

For things like PCIe SATA controllers, you don't need to worry
about setting these address windows, but on most of the ARM/PPC/MIPS
stuff, the mapping windows don't contain valid values after reset,
and the programming has to be done by the bootloader or the kernel.

While the MBUS address map registers are an integral part of each
peripheral's own register set, these MBUS address map windows are
currently programmed directly by platform code, leading to such
gems as arch/arm/mach-orion/addr-map.c and
arch/powerpc/platforms/chrp/pegasos_eth.c.

This patch set is an initial attempt at moving programming of the
MBUS register windows for the set of MBUS peripherals that we currently
have in-tree drivers for from platform code into drivers.

With these patches, info about DRAM target/attribute IDs is prepared
by the platform code as usual, but then passed into platform drivers
via platform device data, instead of programming that data into the
peripherals directly.

This avoids duplicating the window programming code across each
platform that wants to use these peripherals, and avoids exposing
internal peripheral register set details outside of their drivers.

Comments appreciated.


thanks,
Lennert

[PATCH 1/7] introduce mbus DRAM target info abstraction

[Lennert Buytenhek]

Introduce struct mbus_dram_target_info, which will be used for
passing information about the mbus target ID of the DDR unit, and
mbus target attribute, base address and size for each of the DRAM
chip selects from the platform code to peripheral drivers.

Signed-off-by: Lennert Buytenhek <buytenh-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>

Index: linux-2.6.25-rc4/include/linux/mbus.h
===================================================================
--- /dev/null
+++ linux-2.6.25-rc4/include/linux/mbus.h
@@ -0,0 +1,36 @@
+/*
+ * Marvell MBUS common definitions.
+ *
+ * Copyright (C) 2008 Marvell Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __LINUX_MBUS_H
+#define __LINUX_MBUS_H
+
+struct mbus_dram_target_info
+{
+	/*
+	 * The 4-bit MBUS target ID of the DRAM controller.
+	 */
+	u8		mbus_dram_target_id;
+
+	/*
+	 * The base address, size, and MBUS attribute ID for each
+	 * of the possible DRAM chip selects.  Peripherals are
+	 * required to support at least 4 decode windows.
+	 */
+	int		num_cs;
+	struct mbus_dram_window {
+		u8	cs_index;
+		u8	mbus_attr;
+		u32	base;
+		u32	size;
+	} cs[4];
+};
+
+
+#endif
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[PATCH 1/7] introduce mbus DRAM target info abstraction

[Lennert Buytenhek]

Introduce struct mbus_dram_target_info, which will be used for
passing information about the mbus target ID of the DDR unit, and
mbus target attribute, base address and size for each of the DRAM
chip selects from the platform code to peripheral drivers.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>

Index: linux-2.6.25-rc4/include/linux/mbus.h
===================================================================
--- /dev/null
+++ linux-2.6.25-rc4/include/linux/mbus.h
@@ -0,0 +1,36 @@
+/*
+ * Marvell MBUS common definitions.
+ *
+ * Copyright (C) 2008 Marvell Semiconductor
+ *
+ * This file is licensed under the terms of the GNU General Public
+ * License version 2.  This program is licensed "as is" without any
+ * warranty of any kind, whether express or implied.
+ */
+
+#ifndef __LINUX_MBUS_H
+#define __LINUX_MBUS_H
+
+struct mbus_dram_target_info
+{
+	/*
+	 * The 4-bit MBUS target ID of the DRAM controller.
+	 */
+	u8		mbus_dram_target_id;
+
+	/*
+	 * The base address, size, and MBUS attribute ID for each
+	 * of the possible DRAM chip selects.  Peripherals are
+	 * required to support at least 4 decode windows.
+	 */
+	int		num_cs;
+	struct mbus_dram_window {
+		u8	cs_index;
+		u8	mbus_attr;
+		u32	base;
+		u32	size;
+	} cs[4];
+};
+
+
+#endif

[PATCH 2/7] Orion: initialise mbus DRAM target info on boot

[Lennert Buytenhek]

Signed-off-by: Lennert Buytenhek <buytenh-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>

Index: linux-2.6.25-rc4/arch/arm/mach-orion/addr-map.c
===================================================================
--- linux-2.6.25-rc4.orig/arch/arm/mach-orion/addr-map.c
+++ linux-2.6.25-rc4/arch/arm/mach-orion/addr-map.c
@@ -12,6 +12,7 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/mbus.h>
 #include <asm/hardware.h>
 #include <asm/io.h>
 #include "common.h"
@@ -157,6 +158,9 @@
 #define SATA_WIN_BASE(win)	ORION_SATA_REG(0x34 + ((win) * 0x10))
 #define SATA_MAX_WIN		4
 
+
+struct mbus_dram_target_info orion_mbus_dram_info;
+
 static int __init orion_cpu_win_can_remap(int win)
 {
 	u32 dev, rev;
@@ -189,6 +193,7 @@ static void __init setup_cpu_win(int win
 void __init orion_setup_cpu_mbus_bridge(void)
 {
 	int i;
+	int cs;
 
 	/*
 	 * First, disable and clear windows.
@@ -213,6 +218,30 @@ void __init orion_setup_cpu_mbus_bridge(
 		TARGET_PCIE, ATTR_PCIE_MEM, -1);
 	setup_cpu_win(3, ORION_PCI_MEM_PHYS_BASE, ORION_PCI_MEM_SIZE,
 		TARGET_PCI, ATTR_PCI_MEM, -1);
+
+	/*
+	 * Setup MBUS dram target info.
+	 */
+	orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
+
+	for (i = 0, cs = 0; i < 4; i++) {
+		u32 base = readl(DDR_BASE_CS(i));
+		u32 size = readl(DDR_SIZE_CS(i));
+
+		/*
+		 * Chip select enabled?
+		 */
+		if (size & 1) {
+			struct mbus_dram_window *w;
+
+			w = &orion_mbus_dram_info.cs[cs++];
+			w->cs_index = i;
+			w->mbus_attr = 0xf & ~(1 << i);
+			w->base = base & 0xff000000;
+			w->size = (size | 0x00ffffff) + 1;
+		}
+	}
+	orion_mbus_dram_info.num_cs = cs;
 }
 
 void __init orion_setup_dev_boot_win(u32 base, u32 size)
Index: linux-2.6.25-rc4/arch/arm/mach-orion/common.h
===================================================================
--- linux-2.6.25-rc4.orig/arch/arm/mach-orion/common.h
+++ linux-2.6.25-rc4/arch/arm/mach-orion/common.h
@@ -14,6 +14,7 @@ void __init orion_init(void);
  * functions to map its interfaces and by the machine-setup to map its on-
  * board devices. Details in /mach-orion/addr-map.c
  */
+extern struct mbus_dram_target_info orion_mbus_dram_info;
 void orion_setup_cpu_mbus_bridge(void);
 void orion_setup_dev_boot_win(u32 base, u32 size);
 void orion_setup_dev0_win(u32 base, u32 size);
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[PATCH 2/7] Orion: initialise mbus DRAM target info on boot

[Lennert Buytenhek]

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>

Index: linux-2.6.25-rc4/arch/arm/mach-orion/addr-map.c
===================================================================
--- linux-2.6.25-rc4.orig/arch/arm/mach-orion/addr-map.c
+++ linux-2.6.25-rc4/arch/arm/mach-orion/addr-map.c
@@ -12,6 +12,7 @@
 
 #include <linux/kernel.h>
 #include <linux/init.h>
+#include <linux/mbus.h>
 #include <asm/hardware.h>
 #include <asm/io.h>
 #include "common.h"
@@ -157,6 +158,9 @@
 #define SATA_WIN_BASE(win)	ORION_SATA_REG(0x34 + ((win) * 0x10))
 #define SATA_MAX_WIN		4
 
+
+struct mbus_dram_target_info orion_mbus_dram_info;
+
 static int __init orion_cpu_win_can_remap(int win)
 {
 	u32 dev, rev;
@@ -189,6 +193,7 @@ static void __init setup_cpu_win(int win
 void __init orion_setup_cpu_mbus_bridge(void)
 {
 	int i;
+	int cs;
 
 	/*
 	 * First, disable and clear windows.
@@ -213,6 +218,30 @@ void __init orion_setup_cpu_mbus_bridge(
 		TARGET_PCIE, ATTR_PCIE_MEM, -1);
 	setup_cpu_win(3, ORION_PCI_MEM_PHYS_BASE, ORION_PCI_MEM_SIZE,
 		TARGET_PCI, ATTR_PCI_MEM, -1);
+
+	/*
+	 * Setup MBUS dram target info.
+	 */
+	orion_mbus_dram_info.mbus_dram_target_id = TARGET_DDR;
+
+	for (i = 0, cs = 0; i < 4; i++) {
+		u32 base = readl(DDR_BASE_CS(i));
+		u32 size = readl(DDR_SIZE_CS(i));
+
+		/*
+		 * Chip select enabled?
+		 */
+		if (size & 1) {
+			struct mbus_dram_window *w;
+
+			w = &orion_mbus_dram_info.cs[cs++];
+			w->cs_index = i;
+			w->mbus_attr = 0xf & ~(1 << i);
+			w->base = base & 0xff000000;
+			w->size = (size | 0x00ffffff) + 1;
+		}
+	}
+	orion_mbus_dram_info.num_cs = cs;
 }
 
 void __init orion_setup_dev_boot_win(u32 base, u32 size)
Index: linux-2.6.25-rc4/arch/arm/mach-orion/common.h
===================================================================
--- linux-2.6.25-rc4.orig/arch/arm/mach-orion/common.h
+++ linux-2.6.25-rc4/arch/arm/mach-orion/common.h
@@ -14,6 +14,7 @@ void __init orion_init(void);
  * functions to map its interfaces and by the machine-setup to map its on-
  * board devices. Details in /mach-orion/addr-map.c
  */
+extern struct mbus_dram_target_info orion_mbus_dram_info;
 void orion_setup_cpu_mbus_bridge(void);
 void orion_setup_dev_boot_win(u32 base, u32 size);
 void orion_setup_dev0_win(u32 base, u32 size);

[PATCH 3/7] Orion: make PCIe/PCI support use mbus DRAM info

[Lennert Buytenhek]

Make the Orion PCIe/PCI code initialise MBUS decode windows based on
mbus_dram_target_info instead of reading the info from the Orion DDR
unit decode registers directly, and move the window code with the other
PCI code, where it can be called as part of the generic PCIe/PCI init
process.

Signed-off-by: Lennert Buytenhek <buytenh-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>

Index: linux-2.6.25-rc4/arch/arm/mach-orion/addr-map.c
===================================================================
--- linux-2.6.25-rc4.orig/arch/arm/mach-orion/addr-map.c
+++ linux-2.6.25-rc4/arch/arm/mach-orion/addr-map.c
@@ -82,56 +82,6 @@
 #define CPU_WIN_REMAP_HI(n)	ORION_BRIDGE_REG(0x00c | ((n) << 4))
 
 /*
- * PCIE Address Decode Windows registers
- */
-#define PCIE_BAR_CTRL(n)	ORION_PCIE_REG(0x1804 + ((n - 1) * 4))
-#define PCIE_BAR_LO(n)		ORION_PCIE_REG(0x0010 + ((n) * 8))
-#define PCIE_BAR_HI(n)		ORION_PCIE_REG(0x0014 + ((n) * 8))
-#define PCIE_WIN_CTRL(n)	(((n) < 5) ? \
-					ORION_PCIE_REG(0x1820 + ((n) << 4)) : \
-					ORION_PCIE_REG(0x1880))
-#define PCIE_WIN_BASE(n)	(((n) < 5) ? \
-					ORION_PCIE_REG(0x1824 + ((n) << 4)) : \
-					ORION_PCIE_REG(0x1884))
-#define PCIE_WIN_REMAP(n)	(((n) < 5) ? \
-					ORION_PCIE_REG(0x182c + ((n) << 4)) : \
-					ORION_PCIE_REG(0x188c))
-#define PCIE_DEFWIN_CTRL	ORION_PCIE_REG(0x18b0)
-#define PCIE_EXPROM_WIN_CTRL	ORION_PCIE_REG(0x18c0)
-#define PCIE_EXPROM_WIN_REMP	ORION_PCIE_REG(0x18c4)
-#define PCIE_MAX_BARS		3
-#define PCIE_MAX_WINS		6
-
-/*
- * Use PCIE BAR '1' for all DDR banks
- */
-#define PCIE_DRAM_BAR		1
-
-/*
- * PCI Address Decode Windows registers
- */
-#define PCI_BAR_SIZE_DDR_CS(n)	(((n) == 0) ? ORION_PCI_REG(0xc08) : \
-				((n) == 1) ? ORION_PCI_REG(0xd08) :  \
-				((n) == 2) ? ORION_PCI_REG(0xc0c) :  \
-				((n) == 3) ? ORION_PCI_REG(0xd0c) : 0)
-#define PCI_BAR_REMAP_DDR_CS(n)	(((n) ==0) ? ORION_PCI_REG(0xc48) : \
-				((n) == 1) ? ORION_PCI_REG(0xd48) :  \
-				((n) == 2) ? ORION_PCI_REG(0xc4c) :  \
-				((n) == 3) ? ORION_PCI_REG(0xd4c) : 0)
-#define PCI_BAR_ENABLE		ORION_PCI_REG(0xc3c)
-#define PCI_CTRL_BASE_LO(n)	ORION_PCI_REG(0x1e00 | ((n) << 4))
-#define PCI_CTRL_BASE_HI(n)	ORION_PCI_REG(0x1e04 | ((n) << 4))
-#define PCI_CTRL_SIZE(n)	ORION_PCI_REG(0x1e08 | ((n) << 4))
-#define PCI_ADDR_DECODE_CTRL	ORION_PCI_REG(0xd3c)
-
-/*
- * PCI configuration heleprs for BAR settings
- */
-#define PCI_CONF_FUNC_BAR_CS(n)		((n) >> 1)
-#define PCI_CONF_REG_BAR_LO_CS(n)	(((n) & 1) ? 0x18 : 0x10)
-#define PCI_CONF_REG_BAR_HI_CS(n)	(((n) & 1) ? 0x1c : 0x14)
-
-/*
  * Gigabit Ethernet Address Decode Windows registers
  */
 #define ETH_WIN_BASE(win)	ORION_ETH_REG(0x200 + ((win) * 8))
@@ -270,104 +220,6 @@ void __init orion_setup_pcie_wa_win(u32 
 }
 
 
-/*
- * Setup PCIE BARs and Address Decode Wins:
- * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
- * WIN[0-3] -> DRAM bank[0-3]
- */
-void __init orion_setup_pcie_wins(void)
-{
-	u32 base, size, i;
-
-	/*
-	 * First, disable and clear BARs and windows
-	 */
-	for (i = 1; i < PCIE_MAX_BARS; i++) {
-		orion_write(PCIE_BAR_CTRL(i), 0);
-		orion_write(PCIE_BAR_LO(i), 0);
-		orion_write(PCIE_BAR_HI(i), 0);
-	}
-
-	for (i = 0; i < PCIE_MAX_WINS; i++) {
-		orion_write(PCIE_WIN_CTRL(i), 0);
-		orion_write(PCIE_WIN_BASE(i), 0);
-		orion_write(PCIE_WIN_REMAP(i), 0);
-	}
-
-	/*
-	 * Setup windows for DDR banks. Count total DDR size on the fly.
-	 */
-	base = DDR_REG_TO_BASE(orion_read(DDR_BASE_CS(0)));
-	size = 0;
-	for (i = 0; i < DDR_MAX_CS; i++) {
-		u32 bank_base, bank_size;
-		bank_size = orion_read(DDR_SIZE_CS(i));
-		bank_base = orion_read(DDR_BASE_CS(i));
-		if (bank_size & DDR_BANK_EN) {
-			bank_size = DDR_REG_TO_SIZE(bank_size);
-			bank_base = DDR_REG_TO_BASE(bank_base);
-			orion_write(PCIE_WIN_BASE(i), bank_base & 0xffff0000);
-			orion_write(PCIE_WIN_REMAP(i), 0);
-			orion_write(PCIE_WIN_CTRL(i),
-					((bank_size-1) & 0xffff0000) |
-					(ATTR_DDR_CS(i) << 8) |
-					(TARGET_DDR << 4) |
-					(PCIE_DRAM_BAR << 1) | WIN_EN);
-			size += bank_size;
-		}
-	}
-
-	/*
-	 * Setup BAR[1] to all DRAM banks
-	 */
-	orion_write(PCIE_BAR_LO(PCIE_DRAM_BAR), base & 0xffff0000);
-	orion_write(PCIE_BAR_HI(PCIE_DRAM_BAR), 0);
-	orion_write(PCIE_BAR_CTRL(PCIE_DRAM_BAR),
-				((size - 1) & 0xffff0000) | WIN_EN);
-}
-
-void __init orion_setup_pci_wins(void)
-{
-	u32 base, size, i;
-
-	/*
-	 * First, disable windows
-	 */
-	orion_write(PCI_BAR_ENABLE, 0xffffffff);
-
-	/*
-	 * Setup windows for DDR banks.
-	 */
-	for (i = 0; i < DDR_MAX_CS; i++) {
-		base = orion_read(DDR_BASE_CS(i));
-		size = orion_read(DDR_SIZE_CS(i));
-		if (size & DDR_BANK_EN) {
-			u32 bus, dev, func, reg, val;
-			size = DDR_REG_TO_SIZE(size);
-			base = DDR_REG_TO_BASE(base);
-			bus = orion_pci_local_bus_nr();
-			dev = orion_pci_local_dev_nr();
-			func = PCI_CONF_FUNC_BAR_CS(i);
-			reg = PCI_CONF_REG_BAR_LO_CS(i);
-			orion_pci_hw_rd_conf(bus, dev, func, reg, 4, &val);
-			orion_pci_hw_wr_conf(bus, dev, func, reg, 4,
-					(base & 0xfffff000) | (val & 0xfff));
-			reg = PCI_CONF_REG_BAR_HI_CS(i);
-			orion_pci_hw_wr_conf(bus, dev, func, reg, 4, 0);
-			orion_write(PCI_BAR_SIZE_DDR_CS(i),
-					(size - 1) & 0xfffff000);
-			orion_write(PCI_BAR_REMAP_DDR_CS(i),
-					base & 0xfffff000);
-			orion_clrbits(PCI_BAR_ENABLE, (1 << i));
-		}
-	}
-
-	/*
-	 * Disable automatic update of address remaping when writing to BARs
-	 */
-	orion_setbits(PCI_ADDR_DECODE_CTRL, 1);
-}
-
 void __init orion_setup_usb_wins(void)
 {
 	int i;
Index: linux-2.6.25-rc4/arch/arm/mach-orion/common.c
===================================================================
--- linux-2.6.25-rc4.orig/arch/arm/mach-orion/common.c
+++ linux-2.6.25-rc4/arch/arm/mach-orion/common.c
@@ -342,8 +342,6 @@ void __init orion_init(void)
 	orion_setup_cpu_mbus_bridge();
 	orion_setup_usb_wins();
 	orion_setup_eth_wins();
-	orion_setup_pci_wins();
-	orion_setup_pcie_wins();
 	if (dev == MV88F5182_DEV_ID)
 		orion_setup_sata_wins();
 
Index: linux-2.6.25-rc4/arch/arm/mach-orion/common.h
===================================================================
--- linux-2.6.25-rc4.orig/arch/arm/mach-orion/common.h
+++ linux-2.6.25-rc4/arch/arm/mach-orion/common.h
@@ -23,8 +23,6 @@ void orion_setup_dev2_win(u32 base, u32 
 void orion_setup_pcie_wa_win(u32 base, u32 size);
 void orion_setup_eth_wins(void);
 void orion_setup_usb_wins(void);
-void orion_setup_pci_wins(void);
-void orion_setup_pcie_wins(void);
 void orion_setup_sata_wins(void);
 
 /*
@@ -38,11 +36,8 @@ struct pci_bus;
 void orion_pcie_id(u32 *dev, u32 *rev);
 u32 orion_pcie_local_bus_nr(void);
 u32 orion_pci_local_bus_nr(void);
-u32 orion_pci_local_dev_nr(void);
 int orion_pci_sys_setup(int nr, struct pci_sys_data *sys);
 struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
-int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 *val);
-int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 val);
 
 /*
  * Valid GPIO pins according to MPP setup, used by machine-setup.
Index: linux-2.6.25-rc4/arch/arm/mach-orion/pci.c
===================================================================
--- linux-2.6.25-rc4.orig/arch/arm/mach-orion/pci.c
+++ linux-2.6.25-rc4/arch/arm/mach-orion/pci.c
@@ -12,6 +12,7 @@
 
 #include <linux/kernel.h>
 #include <linux/pci.h>
+#include <linux/mbus.h>
 #include <asm/mach/pci.h>
 #include "common.h"
 
@@ -59,6 +60,29 @@
 #define PCIE_CONF_ADDR_EN		(1 << 31)
 
 /*
+ * PCIE Address Decode Windows registers
+ */
+#define PCIE_BAR_CTRL(n)	ORION_PCIE_REG(0x1804 + ((n - 1) * 4))
+#define PCIE_BAR_LO(n)		ORION_PCIE_REG(0x0010 + ((n) * 8))
+#define PCIE_BAR_HI(n)		ORION_PCIE_REG(0x0014 + ((n) * 8))
+#define PCIE_WIN_CTRL(n)	(((n) < 5) ? \
+					ORION_PCIE_REG(0x1820 + ((n) << 4)) : \
+					ORION_PCIE_REG(0x1880))
+#define PCIE_WIN_BASE(n)	(((n) < 5) ? \
+					ORION_PCIE_REG(0x1824 + ((n) << 4)) : \
+					ORION_PCIE_REG(0x1884))
+#define PCIE_WIN_REMAP(n)	(((n) < 5) ? \
+					ORION_PCIE_REG(0x182c + ((n) << 4)) : \
+					ORION_PCIE_REG(0x188c))
+#define PCIE_MAX_BARS		3
+#define PCIE_MAX_WINS		6
+
+/*
+ * Use PCIE BAR '1' for all DDR banks
+ */
+#define PCIE_DRAM_BAR		1
+
+/*
  * PCIE config cycles are done by programming the PCIE_CONF_ADDR register
  * and then reading the PCIE_CONF_DATA register. Need to make sure these
  * transactions are atomic.
@@ -95,6 +119,56 @@ static void orion_pcie_set_bus_nr(int nr
 	orion_setbits(PCIE_STAT, nr << PCIE_STAT_BUS_OFFS);
 }
 
+/*
+ * Setup PCIE BARs and Address Decode Wins:
+ * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
+ * WIN[0-3] -> DRAM bank[0-3]
+ */
+static void orion_setup_pcie_wins(struct mbus_dram_target_info *dram)
+{
+	u32 size;
+	int i;
+
+	/*
+	 * First, disable and clear BARs and windows
+	 */
+	for (i = 1; i < PCIE_MAX_BARS; i++) {
+		writel(0, PCIE_BAR_CTRL(i));
+		writel(0, PCIE_BAR_LO(i));
+		writel(0, PCIE_BAR_HI(i));
+	}
+
+	for (i = 0; i < PCIE_MAX_WINS; i++) {
+		writel(0, PCIE_WIN_CTRL(i));
+		writel(0, PCIE_WIN_BASE(i));
+		writel(0, PCIE_WIN_REMAP(i));
+	}
+
+	/*
+	 * Setup windows for DDR banks. Count total DDR size on the fly.
+	 */
+	size = 0;
+	for (i = 0; i < dram->num_cs; i++) {
+		struct mbus_dram_window *cs = dram->cs + i;
+
+		writel(cs->base & 0xffff0000, PCIE_WIN_BASE(i));
+		writel(0, PCIE_WIN_REMAP(i));
+		writel(((cs->size - 1) & 0xffff0000) |
+			(cs->mbus_attr << 8) |
+			(dram->mbus_dram_target_id << 4) |
+			(PCIE_DRAM_BAR << 1) | 1, PCIE_WIN_CTRL(i));
+
+		size += cs->size;
+	}
+
+	/*
+	 * Setup BAR[1] to all DRAM banks
+	 */
+	writel(dram->cs[0].base, PCIE_BAR_LO(PCIE_DRAM_BAR));
+	writel(0, PCIE_BAR_HI(PCIE_DRAM_BAR));
+	writel(((size - 1) & 0xffff0000) | 1, PCIE_BAR_CTRL(PCIE_DRAM_BAR));
+}
+
 static void orion_pcie_master_slave_enable(void)
 {
 	orion_setbits(PCIE_CMD_STAT, PCI_COMMAND_MASTER |
@@ -220,6 +294,11 @@ static int orion_pcie_setup(struct pci_s
 	struct resource *res;
 
 	/*
+	 * Point PCIe unit MBUS decode windows to DRAM space.
+	 */
+	orion_setup_pcie_wins(&orion_mbus_dram_info);
+
+	/*
 	 * Master + Slave enable
 	 */
 	orion_pcie_master_slave_enable();
@@ -311,6 +390,27 @@ static int orion_pcie_setup(struct pci_s
 #define PCIX_STAT_BUS_MASK		(0xff << PCIX_STAT_BUS_OFFS)
 
 /*
+ * PCI Address Decode Windows registers
+ */
+#define PCI_BAR_SIZE_DDR_CS(n)	(((n) == 0) ? ORION_PCI_REG(0xc08) : \
+				((n) == 1) ? ORION_PCI_REG(0xd08) :  \
+				((n) == 2) ? ORION_PCI_REG(0xc0c) :  \
+				((n) == 3) ? ORION_PCI_REG(0xd0c) : 0)
+#define PCI_BAR_REMAP_DDR_CS(n)	(((n) ==0) ? ORION_PCI_REG(0xc48) :  \
+				((n) == 1) ? ORION_PCI_REG(0xd48) :  \
+				((n) == 2) ? ORION_PCI_REG(0xc4c) :  \
+				((n) == 3) ? ORION_PCI_REG(0xd4c) : 0)
+#define PCI_BAR_ENABLE		ORION_PCI_REG(0xc3c)
+#define PCI_ADDR_DECODE_CTRL	ORION_PCI_REG(0xd3c)
+
+/*
+ * PCI configuration helpers for BAR settings
+ */
+#define PCI_CONF_FUNC_BAR_CS(n)		((n) >> 1)
+#define PCI_CONF_REG_BAR_LO_CS(n)	(((n) & 1) ? 0x18 : 0x10)
+#define PCI_CONF_REG_BAR_HI_CS(n)	(((n) & 1) ? 0x1c : 0x14)
+
+/*
  * PCI config cycles are done by programming the PCI_CONF_ADDR register
  * and then reading the PCI_CONF_DATA register. Need to make sure these
  * transactions are atomic.
@@ -323,13 +423,13 @@ u32 orion_pci_local_bus_nr(void)
 	return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
 }
 
-u32 orion_pci_local_dev_nr(void)
+static u32 orion_pci_local_dev_nr(void)
 {
 	u32 conf = orion_read(PCI_P2P_CONF);
 	return((conf & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS);
 }
 
-int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func,
+static int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func,
 					u32 where, u32 size, u32 *val)
 {
 	unsigned long flags;
@@ -351,7 +451,7 @@ int orion_pci_hw_rd_conf(u32 bus, u32 de
 	return PCIBIOS_SUCCESSFUL;
 }
 
-int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func,
+static int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func,
 					u32 where, u32 size, u32 val)
 {
 	unsigned long flags;
@@ -451,11 +551,76 @@ static void orion_pci_master_slave_enabl
 	orion_pci_hw_wr_conf(bus_nr, dev_nr, func, reg, 4, val | 0x7);
 }
 
+static void orion_setup_pci_wins(struct mbus_dram_target_info *dram)
+{
+	u32 win_enable;
+	u32 bus;
+	u32 dev;
+	int i;
+
+	/*
+	 * First, disable windows.
+	 */
+	win_enable = 0xffffffff;
+	orion_write(PCI_BAR_ENABLE, win_enable);
+
+	/*
+	 * Setup windows for DDR banks.
+	 */
+	bus = orion_pci_local_bus_nr();
+	dev = orion_pci_local_dev_nr();
+
+	for (i = 0; i < dram->num_cs; i++) {
+		struct mbus_dram_window *cs = dram->cs + i;
+		u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
+		u32 reg;
+		u32 val;
+
+		/*
+		 * Write DRAM bank base address register.
+		 */
+		reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
+		orion_pci_hw_rd_conf(bus, dev, func, reg, 4, &val);
+		val = (cs->base & 0xfffff000) | (val & 0xfff);
+		orion_pci_hw_wr_conf(bus, dev, func, reg, 4, val);
+
+		/*
+		 * Write DRAM bank size register.
+		 */
+		reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
+		orion_pci_hw_wr_conf(bus, dev, func, reg, 4, 0);
+		orion_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index),
+				(cs->size - 1) & 0xfffff000);
+		orion_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index),
+				cs->base & 0xfffff000);
+
+		/*
+		 * Enable decode window for this chip select.
+		 */
+		win_enable &= ~(1 << cs->cs_index);
+	}
+
+	/*
+	 * Re-enable decode windows.
+	 */
+	orion_write(PCI_BAR_ENABLE, win_enable);
+
+	/*
+	 * Disable automatic update of address remaping when writing to BARs.
+	 */
+	orion_setbits(PCI_ADDR_DECODE_CTRL, 1);
+}
+
 static int orion_pci_setup(struct pci_sys_data *sys)
 {
 	struct resource *res;
 
 	/*
+	 * Point PCI unit MBUS decode windows to DRAM space.
+	 */
+	orion_setup_pci_wins(&orion_mbus_dram_info);
+
+	/*
 	 * Master + Slave enable
 	 */
 	orion_pci_master_slave_enable();
--
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[PATCH 3/7] Orion: make PCIe/PCI support use mbus DRAM info

[Lennert Buytenhek]

Make the Orion PCIe/PCI code initialise MBUS decode windows based on
mbus_dram_target_info instead of reading the info from the Orion DDR
unit decode registers directly, and move the window code with the other
PCI code, where it can be called as part of the generic PCIe/PCI init
process.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>

Index: linux-2.6.25-rc4/arch/arm/mach-orion/addr-map.c
===================================================================
--- linux-2.6.25-rc4.orig/arch/arm/mach-orion/addr-map.c
+++ linux-2.6.25-rc4/arch/arm/mach-orion/addr-map.c
@@ -82,56 +82,6 @@
 #define CPU_WIN_REMAP_HI(n)	ORION_BRIDGE_REG(0x00c | ((n) << 4))
 
 /*
- * PCIE Address Decode Windows registers
- */
-#define PCIE_BAR_CTRL(n)	ORION_PCIE_REG(0x1804 + ((n - 1) * 4))
-#define PCIE_BAR_LO(n)		ORION_PCIE_REG(0x0010 + ((n) * 8))
-#define PCIE_BAR_HI(n)		ORION_PCIE_REG(0x0014 + ((n) * 8))
-#define PCIE_WIN_CTRL(n)	(((n) < 5) ? \
-					ORION_PCIE_REG(0x1820 + ((n) << 4)) : \
-					ORION_PCIE_REG(0x1880))
-#define PCIE_WIN_BASE(n)	(((n) < 5) ? \
-					ORION_PCIE_REG(0x1824 + ((n) << 4)) : \
-					ORION_PCIE_REG(0x1884))
-#define PCIE_WIN_REMAP(n)	(((n) < 5) ? \
-					ORION_PCIE_REG(0x182c + ((n) << 4)) : \
-					ORION_PCIE_REG(0x188c))
-#define PCIE_DEFWIN_CTRL	ORION_PCIE_REG(0x18b0)
-#define PCIE_EXPROM_WIN_CTRL	ORION_PCIE_REG(0x18c0)
-#define PCIE_EXPROM_WIN_REMP	ORION_PCIE_REG(0x18c4)
-#define PCIE_MAX_BARS		3
-#define PCIE_MAX_WINS		6
-
-/*
- * Use PCIE BAR '1' for all DDR banks
- */
-#define PCIE_DRAM_BAR		1
-
-/*
- * PCI Address Decode Windows registers
- */
-#define PCI_BAR_SIZE_DDR_CS(n)	(((n) == 0) ? ORION_PCI_REG(0xc08) : \
-				((n) == 1) ? ORION_PCI_REG(0xd08) :  \
-				((n) == 2) ? ORION_PCI_REG(0xc0c) :  \
-				((n) == 3) ? ORION_PCI_REG(0xd0c) : 0)
-#define PCI_BAR_REMAP_DDR_CS(n)	(((n) ==0) ? ORION_PCI_REG(0xc48) : \
-				((n) == 1) ? ORION_PCI_REG(0xd48) :  \
-				((n) == 2) ? ORION_PCI_REG(0xc4c) :  \
-				((n) == 3) ? ORION_PCI_REG(0xd4c) : 0)
-#define PCI_BAR_ENABLE		ORION_PCI_REG(0xc3c)
-#define PCI_CTRL_BASE_LO(n)	ORION_PCI_REG(0x1e00 | ((n) << 4))
-#define PCI_CTRL_BASE_HI(n)	ORION_PCI_REG(0x1e04 | ((n) << 4))
-#define PCI_CTRL_SIZE(n)	ORION_PCI_REG(0x1e08 | ((n) << 4))
-#define PCI_ADDR_DECODE_CTRL	ORION_PCI_REG(0xd3c)
-
-/*
- * PCI configuration heleprs for BAR settings
- */
-#define PCI_CONF_FUNC_BAR_CS(n)		((n) >> 1)
-#define PCI_CONF_REG_BAR_LO_CS(n)	(((n) & 1) ? 0x18 : 0x10)
-#define PCI_CONF_REG_BAR_HI_CS(n)	(((n) & 1) ? 0x1c : 0x14)
-
-/*
  * Gigabit Ethernet Address Decode Windows registers
  */
 #define ETH_WIN_BASE(win)	ORION_ETH_REG(0x200 + ((win) * 8))
@@ -270,104 +220,6 @@ void __init orion_setup_pcie_wa_win(u32 
 }
 
 
-/*
- * Setup PCIE BARs and Address Decode Wins:
- * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
- * WIN[0-3] -> DRAM bank[0-3]
- */
-void __init orion_setup_pcie_wins(void)
-{
-	u32 base, size, i;
-
-	/*
-	 * First, disable and clear BARs and windows
-	 */
-	for (i = 1; i < PCIE_MAX_BARS; i++) {
-		orion_write(PCIE_BAR_CTRL(i), 0);
-		orion_write(PCIE_BAR_LO(i), 0);
-		orion_write(PCIE_BAR_HI(i), 0);
-	}
-
-	for (i = 0; i < PCIE_MAX_WINS; i++) {
-		orion_write(PCIE_WIN_CTRL(i), 0);
-		orion_write(PCIE_WIN_BASE(i), 0);
-		orion_write(PCIE_WIN_REMAP(i), 0);
-	}
-
-	/*
-	 * Setup windows for DDR banks. Count total DDR size on the fly.
-	 */
-	base = DDR_REG_TO_BASE(orion_read(DDR_BASE_CS(0)));
-	size = 0;
-	for (i = 0; i < DDR_MAX_CS; i++) {
-		u32 bank_base, bank_size;
-		bank_size = orion_read(DDR_SIZE_CS(i));
-		bank_base = orion_read(DDR_BASE_CS(i));
-		if (bank_size & DDR_BANK_EN) {
-			bank_size = DDR_REG_TO_SIZE(bank_size);
-			bank_base = DDR_REG_TO_BASE(bank_base);
-			orion_write(PCIE_WIN_BASE(i), bank_base & 0xffff0000);
-			orion_write(PCIE_WIN_REMAP(i), 0);
-			orion_write(PCIE_WIN_CTRL(i),
-					((bank_size-1) & 0xffff0000) |
-					(ATTR_DDR_CS(i) << 8) |
-					(TARGET_DDR << 4) |
-					(PCIE_DRAM_BAR << 1) | WIN_EN);
-			size += bank_size;
-		}
-	}
-
-	/*
-	 * Setup BAR[1] to all DRAM banks
-	 */
-	orion_write(PCIE_BAR_LO(PCIE_DRAM_BAR), base & 0xffff0000);
-	orion_write(PCIE_BAR_HI(PCIE_DRAM_BAR), 0);
-	orion_write(PCIE_BAR_CTRL(PCIE_DRAM_BAR),
-				((size - 1) & 0xffff0000) | WIN_EN);
-}
-
-void __init orion_setup_pci_wins(void)
-{
-	u32 base, size, i;
-
-	/*
-	 * First, disable windows
-	 */
-	orion_write(PCI_BAR_ENABLE, 0xffffffff);
-
-	/*
-	 * Setup windows for DDR banks.
-	 */
-	for (i = 0; i < DDR_MAX_CS; i++) {
-		base = orion_read(DDR_BASE_CS(i));
-		size = orion_read(DDR_SIZE_CS(i));
-		if (size & DDR_BANK_EN) {
-			u32 bus, dev, func, reg, val;
-			size = DDR_REG_TO_SIZE(size);
-			base = DDR_REG_TO_BASE(base);
-			bus = orion_pci_local_bus_nr();
-			dev = orion_pci_local_dev_nr();
-			func = PCI_CONF_FUNC_BAR_CS(i);
-			reg = PCI_CONF_REG_BAR_LO_CS(i);
-			orion_pci_hw_rd_conf(bus, dev, func, reg, 4, &val);
-			orion_pci_hw_wr_conf(bus, dev, func, reg, 4,
-					(base & 0xfffff000) | (val & 0xfff));
-			reg = PCI_CONF_REG_BAR_HI_CS(i);
-			orion_pci_hw_wr_conf(bus, dev, func, reg, 4, 0);
-			orion_write(PCI_BAR_SIZE_DDR_CS(i),
-					(size - 1) & 0xfffff000);
-			orion_write(PCI_BAR_REMAP_DDR_CS(i),
-					base & 0xfffff000);
-			orion_clrbits(PCI_BAR_ENABLE, (1 << i));
-		}
-	}
-
-	/*
-	 * Disable automatic update of address remaping when writing to BARs
-	 */
-	orion_setbits(PCI_ADDR_DECODE_CTRL, 1);
-}
-
 void __init orion_setup_usb_wins(void)
 {
 	int i;
Index: linux-2.6.25-rc4/arch/arm/mach-orion/common.c
===================================================================
--- linux-2.6.25-rc4.orig/arch/arm/mach-orion/common.c
+++ linux-2.6.25-rc4/arch/arm/mach-orion/common.c
@@ -342,8 +342,6 @@ void __init orion_init(void)
 	orion_setup_cpu_mbus_bridge();
 	orion_setup_usb_wins();
 	orion_setup_eth_wins();
-	orion_setup_pci_wins();
-	orion_setup_pcie_wins();
 	if (dev == MV88F5182_DEV_ID)
 		orion_setup_sata_wins();
 
Index: linux-2.6.25-rc4/arch/arm/mach-orion/common.h
===================================================================
--- linux-2.6.25-rc4.orig/arch/arm/mach-orion/common.h
+++ linux-2.6.25-rc4/arch/arm/mach-orion/common.h
@@ -23,8 +23,6 @@ void orion_setup_dev2_win(u32 base, u32 
 void orion_setup_pcie_wa_win(u32 base, u32 size);
 void orion_setup_eth_wins(void);
 void orion_setup_usb_wins(void);
-void orion_setup_pci_wins(void);
-void orion_setup_pcie_wins(void);
 void orion_setup_sata_wins(void);
 
 /*
@@ -38,11 +36,8 @@ struct pci_bus;
 void orion_pcie_id(u32 *dev, u32 *rev);
 u32 orion_pcie_local_bus_nr(void);
 u32 orion_pci_local_bus_nr(void);
-u32 orion_pci_local_dev_nr(void);
 int orion_pci_sys_setup(int nr, struct pci_sys_data *sys);
 struct pci_bus *orion_pci_sys_scan_bus(int nr, struct pci_sys_data *sys);
-int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 *val);
-int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func, u32 where, u32 size, u32 val);
 
 /*
  * Valid GPIO pins according to MPP setup, used by machine-setup.
Index: linux-2.6.25-rc4/arch/arm/mach-orion/pci.c
===================================================================
--- linux-2.6.25-rc4.orig/arch/arm/mach-orion/pci.c
+++ linux-2.6.25-rc4/arch/arm/mach-orion/pci.c
@@ -12,6 +12,7 @@
 
 #include <linux/kernel.h>
 #include <linux/pci.h>
+#include <linux/mbus.h>
 #include <asm/mach/pci.h>
 #include "common.h"
 
@@ -59,6 +60,29 @@
 #define PCIE_CONF_ADDR_EN		(1 << 31)
 
 /*
+ * PCIE Address Decode Windows registers
+ */
+#define PCIE_BAR_CTRL(n)	ORION_PCIE_REG(0x1804 + ((n - 1) * 4))
+#define PCIE_BAR_LO(n)		ORION_PCIE_REG(0x0010 + ((n) * 8))
+#define PCIE_BAR_HI(n)		ORION_PCIE_REG(0x0014 + ((n) * 8))
+#define PCIE_WIN_CTRL(n)	(((n) < 5) ? \
+					ORION_PCIE_REG(0x1820 + ((n) << 4)) : \
+					ORION_PCIE_REG(0x1880))
+#define PCIE_WIN_BASE(n)	(((n) < 5) ? \
+					ORION_PCIE_REG(0x1824 + ((n) << 4)) : \
+					ORION_PCIE_REG(0x1884))
+#define PCIE_WIN_REMAP(n)	(((n) < 5) ? \
+					ORION_PCIE_REG(0x182c + ((n) << 4)) : \
+					ORION_PCIE_REG(0x188c))
+#define PCIE_MAX_BARS		3
+#define PCIE_MAX_WINS		6
+
+/*
+ * Use PCIE BAR '1' for all DDR banks
+ */
+#define PCIE_DRAM_BAR		1
+
+/*
  * PCIE config cycles are done by programming the PCIE_CONF_ADDR register
  * and then reading the PCIE_CONF_DATA register. Need to make sure these
  * transactions are atomic.
@@ -95,6 +119,56 @@ static void orion_pcie_set_bus_nr(int nr
 	orion_setbits(PCIE_STAT, nr << PCIE_STAT_BUS_OFFS);
 }
 
+/*
+ * Setup PCIE BARs and Address Decode Wins:
+ * BAR[0,2] -> disabled, BAR[1] -> covers all DRAM banks
+ * WIN[0-3] -> DRAM bank[0-3]
+ */
+static void orion_setup_pcie_wins(struct mbus_dram_target_info *dram)
+{
+	u32 size;
+	int i;
+
+	/*
+	 * First, disable and clear BARs and windows
+	 */
+	for (i = 1; i < PCIE_MAX_BARS; i++) {
+		writel(0, PCIE_BAR_CTRL(i));
+		writel(0, PCIE_BAR_LO(i));
+		writel(0, PCIE_BAR_HI(i));
+	}
+
+	for (i = 0; i < PCIE_MAX_WINS; i++) {
+		writel(0, PCIE_WIN_CTRL(i));
+		writel(0, PCIE_WIN_BASE(i));
+		writel(0, PCIE_WIN_REMAP(i));
+	}
+
+	/*
+	 * Setup windows for DDR banks. Count total DDR size on the fly.
+	 */
+	size = 0;
+	for (i = 0; i < dram->num_cs; i++) {
+		struct mbus_dram_window *cs = dram->cs + i;
+
+		writel(cs->base & 0xffff0000, PCIE_WIN_BASE(i));
+		writel(0, PCIE_WIN_REMAP(i));
+		writel(((cs->size - 1) & 0xffff0000) |
+			(cs->mbus_attr << 8) |
+			(dram->mbus_dram_target_id << 4) |
+			(PCIE_DRAM_BAR << 1) | 1, PCIE_WIN_CTRL(i));
+
+		size += cs->size;
+	}
+
+	/*
+	 * Setup BAR[1] to all DRAM banks
+	 */
+	writel(dram->cs[0].base, PCIE_BAR_LO(PCIE_DRAM_BAR));
+	writel(0, PCIE_BAR_HI(PCIE_DRAM_BAR));
+	writel(((size - 1) & 0xffff0000) | 1, PCIE_BAR_CTRL(PCIE_DRAM_BAR));
+}
+
 static void orion_pcie_master_slave_enable(void)
 {
 	orion_setbits(PCIE_CMD_STAT, PCI_COMMAND_MASTER |
@@ -220,6 +294,11 @@ static int orion_pcie_setup(struct pci_s
 	struct resource *res;
 
 	/*
+	 * Point PCIe unit MBUS decode windows to DRAM space.
+	 */
+	orion_setup_pcie_wins(&orion_mbus_dram_info);
+
+	/*
 	 * Master + Slave enable
 	 */
 	orion_pcie_master_slave_enable();
@@ -311,6 +390,27 @@ static int orion_pcie_setup(struct pci_s
 #define PCIX_STAT_BUS_MASK		(0xff << PCIX_STAT_BUS_OFFS)
 
 /*
+ * PCI Address Decode Windows registers
+ */
+#define PCI_BAR_SIZE_DDR_CS(n)	(((n) == 0) ? ORION_PCI_REG(0xc08) : \
+				((n) == 1) ? ORION_PCI_REG(0xd08) :  \
+				((n) == 2) ? ORION_PCI_REG(0xc0c) :  \
+				((n) == 3) ? ORION_PCI_REG(0xd0c) : 0)
+#define PCI_BAR_REMAP_DDR_CS(n)	(((n) ==0) ? ORION_PCI_REG(0xc48) :  \
+				((n) == 1) ? ORION_PCI_REG(0xd48) :  \
+				((n) == 2) ? ORION_PCI_REG(0xc4c) :  \
+				((n) == 3) ? ORION_PCI_REG(0xd4c) : 0)
+#define PCI_BAR_ENABLE		ORION_PCI_REG(0xc3c)
+#define PCI_ADDR_DECODE_CTRL	ORION_PCI_REG(0xd3c)
+
+/*
+ * PCI configuration helpers for BAR settings
+ */
+#define PCI_CONF_FUNC_BAR_CS(n)		((n) >> 1)
+#define PCI_CONF_REG_BAR_LO_CS(n)	(((n) & 1) ? 0x18 : 0x10)
+#define PCI_CONF_REG_BAR_HI_CS(n)	(((n) & 1) ? 0x1c : 0x14)
+
+/*
  * PCI config cycles are done by programming the PCI_CONF_ADDR register
  * and then reading the PCI_CONF_DATA register. Need to make sure these
  * transactions are atomic.
@@ -323,13 +423,13 @@ u32 orion_pci_local_bus_nr(void)
 	return((conf & PCI_P2P_BUS_MASK) >> PCI_P2P_BUS_OFFS);
 }
 
-u32 orion_pci_local_dev_nr(void)
+static u32 orion_pci_local_dev_nr(void)
 {
 	u32 conf = orion_read(PCI_P2P_CONF);
 	return((conf & PCI_P2P_DEV_MASK) >> PCI_P2P_DEV_OFFS);
 }
 
-int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func,
+static int orion_pci_hw_rd_conf(u32 bus, u32 dev, u32 func,
 					u32 where, u32 size, u32 *val)
 {
 	unsigned long flags;
@@ -351,7 +451,7 @@ int orion_pci_hw_rd_conf(u32 bus, u32 de
 	return PCIBIOS_SUCCESSFUL;
 }
 
-int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func,
+static int orion_pci_hw_wr_conf(u32 bus, u32 dev, u32 func,
 					u32 where, u32 size, u32 val)
 {
 	unsigned long flags;
@@ -451,11 +551,76 @@ static void orion_pci_master_slave_enabl
 	orion_pci_hw_wr_conf(bus_nr, dev_nr, func, reg, 4, val | 0x7);
 }
 
+static void orion_setup_pci_wins(struct mbus_dram_target_info *dram)
+{
+	u32 win_enable;
+	u32 bus;
+	u32 dev;
+	int i;
+
+	/*
+	 * First, disable windows.
+	 */
+	win_enable = 0xffffffff;
+	orion_write(PCI_BAR_ENABLE, win_enable);
+
+	/*
+	 * Setup windows for DDR banks.
+	 */
+	bus = orion_pci_local_bus_nr();
+	dev = orion_pci_local_dev_nr();
+
+	for (i = 0; i < dram->num_cs; i++) {
+		struct mbus_dram_window *cs = dram->cs + i;
+		u32 func = PCI_CONF_FUNC_BAR_CS(cs->cs_index);
+		u32 reg;
+		u32 val;
+
+		/*
+		 * Write DRAM bank base address register.
+		 */
+		reg = PCI_CONF_REG_BAR_LO_CS(cs->cs_index);
+		orion_pci_hw_rd_conf(bus, dev, func, reg, 4, &val);
+		val = (cs->base & 0xfffff000) | (val & 0xfff);
+		orion_pci_hw_wr_conf(bus, dev, func, reg, 4, val);
+
+		/*
+		 * Write DRAM bank size register.
+		 */
+		reg = PCI_CONF_REG_BAR_HI_CS(cs->cs_index);
+		orion_pci_hw_wr_conf(bus, dev, func, reg, 4, 0);
+		orion_write(PCI_BAR_SIZE_DDR_CS(cs->cs_index),
+				(cs->size - 1) & 0xfffff000);
+		orion_write(PCI_BAR_REMAP_DDR_CS(cs->cs_index),
+				cs->base & 0xfffff000);
+
+		/*
+		 * Enable decode window for this chip select.
+		 */
+		win_enable &= ~(1 << cs->cs_index);
+	}
+
+	/*
+	 * Re-enable decode windows.
+	 */
+	orion_write(PCI_BAR_ENABLE, win_enable);
+
+	/*
+	 * Disable automatic update of address remaping when writing to BARs.
+	 */
+	orion_setbits(PCI_ADDR_DECODE_CTRL, 1);
+}
+
 static int orion_pci_setup(struct pci_sys_data *sys)
 {
 	struct resource *res;
 
 	/*
+	 * Point PCI unit MBUS decode windows to DRAM space.
+	 */
+	orion_setup_pci_wins(&orion_mbus_dram_info);
+
+	/*
 	 * Master + Slave enable
 	 */
 	orion_pci_master_slave_enable();

[PATCH 4/7] ehci-orion: mbus decode window support

[Lennert Buytenhek]

Make it possible to pass mbus_dram_target_info to the ehci-orion
driver via the platform data, and make the ehci-orion driver
program the window registers based on this data if it is passed in.

Signed-off-by: Lennert Buytenhek <buytenh-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>

Index: linux-2.6.25-rc4/drivers/usb/host/ehci-orion.c
===================================================================
--- linux-2.6.25-rc4.orig/drivers/usb/host/ehci-orion.c
+++ linux-2.6.25-rc4/drivers/usb/host/ehci-orion.c
@@ -11,15 +11,19 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/mbus.h>
 #include <asm/arch/orion.h>
+#include <asm/arch/platform.h>
 
 #define rdl(off)	__raw_readl(hcd->regs + (off))
 #define wrl(off, val)	__raw_writel((val), hcd->regs + (off))
 
-#define USB_CAUSE		0x310
-#define USB_MASK		0x314
 #define USB_CMD			0x140
 #define USB_MODE		0x1a8
+#define USB_CAUSE		0x310
+#define USB_MASK		0x314
+#define USB_WINDOW_CTRL(i)	(0x320 + ((i) << 4))
+#define USB_WINDOW_BASE(i)	(0x324 + ((i) << 4))
 #define USB_IPG			0x360
 #define USB_PHY_PWR_CTRL	0x400
 #define USB_PHY_TX_CTRL		0x420
@@ -162,8 +166,30 @@ static const struct hc_driver ehci_orion
 	.bus_resume = ehci_bus_resume,
 };
 
+static void __init
+ehci_orion_conf_mbus_windows(struct usb_hcd *hcd,
+				struct mbus_dram_target_info *dram)
+{
+	int i;
+
+	for (i = 0; i < 4; i++) {
+		wrl(USB_WINDOW_CTRL(i), 0);
+		wrl(USB_WINDOW_BASE(i), 0);
+	}
+
+	for (i = 0; i < dram->num_cs; i++) {
+		struct mbus_dram_window *cs = dram->cs + i;
+
+		wrl(USB_WINDOW_CTRL(i), ((cs->size - 1) & 0xffff0000) |
+					(cs->mbus_attr << 8) |
+					(dram->mbus_dram_target_id << 4) | 1);
+		wrl(USB_WINDOW_BASE(i), cs->base);
+	}
+}
+
 static int __init ehci_orion_drv_probe(struct platform_device *pdev)
 {
+	struct orion_ehci_data *pd = pdev->dev.platform_data;
 	struct resource *res;
 	struct usb_hcd *hcd;
 	struct ehci_hcd *ehci;
@@ -227,6 +253,12 @@ static int __init ehci_orion_drv_probe(s
 	ehci->sbrn = 0x20;
 
 	/*
+	 * (Re-)program MBUS remapping windows if we are asked to.
+	 */
+	if (pd != NULL && pd->dram != NULL)
+		ehci_orion_conf_mbus_windows(hcd, pd->dram);
+
+	/*
 	 * setup Orion USB controller
 	 */
 	orion_usb_setup(hcd);
Index: linux-2.6.25-rc4/include/asm-arm/arch-orion/platform.h
===================================================================
--- linux-2.6.25-rc4.orig/include/asm-arm/arch-orion/platform.h
+++ linux-2.6.25-rc4/include/asm-arm/arch-orion/platform.h
@@ -12,6 +12,14 @@
 #define __ASM_ARCH_PLATFORM_H__
 
 /*
+ * Orion EHCI platform driver data.
+ */
+struct orion_ehci_data {
+	struct mbus_dram_target_info	*dram;
+};
+
+
+/*
  * Device bus NAND private data
  */
 struct orion_nand_data {
@@ -22,4 +30,5 @@ struct orion_nand_data {
 	u8 width;	/* buswidth */
 };
 
+
 #endif
--
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[PATCH 4/7] ehci-orion: mbus decode window support

[Lennert Buytenhek]

Make it possible to pass mbus_dram_target_info to the ehci-orion
driver via the platform data, and make the ehci-orion driver
program the window registers based on this data if it is passed in.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>

Index: linux-2.6.25-rc4/drivers/usb/host/ehci-orion.c
===================================================================
--- linux-2.6.25-rc4.orig/drivers/usb/host/ehci-orion.c
+++ linux-2.6.25-rc4/drivers/usb/host/ehci-orion.c
@@ -11,15 +11,19 @@
 #include <linux/kernel.h>
 #include <linux/module.h>
 #include <linux/platform_device.h>
+#include <linux/mbus.h>
 #include <asm/arch/orion.h>
+#include <asm/arch/platform.h>
 
 #define rdl(off)	__raw_readl(hcd->regs + (off))
 #define wrl(off, val)	__raw_writel((val), hcd->regs + (off))
 
-#define USB_CAUSE		0x310
-#define USB_MASK		0x314
 #define USB_CMD			0x140
 #define USB_MODE		0x1a8
+#define USB_CAUSE		0x310
+#define USB_MASK		0x314
+#define USB_WINDOW_CTRL(i)	(0x320 + ((i) << 4))
+#define USB_WINDOW_BASE(i)	(0x324 + ((i) << 4))
 #define USB_IPG			0x360
 #define USB_PHY_PWR_CTRL	0x400
 #define USB_PHY_TX_CTRL		0x420
@@ -162,8 +166,30 @@ static const struct hc_driver ehci_orion
 	.bus_resume = ehci_bus_resume,
 };
 
+static void __init
+ehci_orion_conf_mbus_windows(struct usb_hcd *hcd,
+				struct mbus_dram_target_info *dram)
+{
+	int i;
+
+	for (i = 0; i < 4; i++) {
+		wrl(USB_WINDOW_CTRL(i), 0);
+		wrl(USB_WINDOW_BASE(i), 0);
+	}
+
+	for (i = 0; i < dram->num_cs; i++) {
+		struct mbus_dram_window *cs = dram->cs + i;
+
+		wrl(USB_WINDOW_CTRL(i), ((cs->size - 1) & 0xffff0000) |
+					(cs->mbus_attr << 8) |
+					(dram->mbus_dram_target_id << 4) | 1);
+		wrl(USB_WINDOW_BASE(i), cs->base);
+	}
+}
+
 static int __init ehci_orion_drv_probe(struct platform_device *pdev)
 {
+	struct orion_ehci_data *pd = pdev->dev.platform_data;
 	struct resource *res;
 	struct usb_hcd *hcd;
 	struct ehci_hcd *ehci;
@@ -227,6 +253,12 @@ static int __init ehci_orion_drv_probe(s
 	ehci->sbrn = 0x20;
 
 	/*
+	 * (Re-)program MBUS remapping windows if we are asked to.
+	 */
+	if (pd != NULL && pd->dram != NULL)
+		ehci_orion_conf_mbus_windows(hcd, pd->dram);
+
+	/*
 	 * setup Orion USB controller
 	 */
 	orion_usb_setup(hcd);
Index: linux-2.6.25-rc4/include/asm-arm/arch-orion/platform.h
===================================================================
--- linux-2.6.25-rc4.orig/include/asm-arm/arch-orion/platform.h
+++ linux-2.6.25-rc4/include/asm-arm/arch-orion/platform.h
@@ -12,6 +12,14 @@
 #define __ASM_ARCH_PLATFORM_H__
 
 /*
+ * Orion EHCI platform driver data.
+ */
+struct orion_ehci_data {
+	struct mbus_dram_target_info	*dram;
+};
+
+
+/*
  * Device bus NAND private data
  */
 struct orion_nand_data {
@@ -22,4 +30,5 @@ struct orion_nand_data {
 	u8 width;	/* buswidth */
 };
 
+
 #endif

[PATCH 5/7] mv643xx_eth: mbus decode window support

[Lennert Buytenhek]

Make it possible to pass mbus_dram_target_info to the mv643xx_eth
driver via the platform data, and make the mv643xx_eth driver
program the window registers based on this data if it is passed in.

Signed-off-by: Lennert Buytenhek <buytenh-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>

Index: linux-2.6.25-rc4/drivers/net/mv643xx_eth.c
===================================================================
--- linux-2.6.25-rc4.orig/drivers/net/mv643xx_eth.c
+++ linux-2.6.25-rc4/drivers/net/mv643xx_eth.c
@@ -91,6 +91,11 @@
  */
 #define PHY_ADDR_REG				0x0000
 #define SMI_REG					0x0004
+#define WINDOW_BASE(i)				(0x0200 + ((i) << 3))
+#define WINDOW_SIZE(i)				(0x0204 + ((i) << 3))
+#define WINDOW_REMAP_HIGH(i)			(0x0280 + ((i) << 2))
+#define WINDOW_BAR_ENABLE			0x0290
+#define WINDOW_PROTECT(i)			(0x0294 + ((i) << 4))
 
 /*
  * Per-port registers.
@@ -514,6 +519,8 @@ struct mv643xx_shared_private {
 	spinlock_t phy_lock;
 
 	unsigned int t_clk;
+
+	u32 win_protect;
 };
 
 struct mv643xx_private {
@@ -1892,6 +1899,9 @@ static int mv643xx_eth_probe(struct plat
 	mp->shared = platform_get_drvdata(pd->shared);
 	port_num = mp->port_num = pd->port_number;
 
+	if (mp->shared->win_protect)
+		wrl(mp, WINDOW_PROTECT(port_num), mp->shared->win_protect);
+
 	mp->shared_smi = mp->shared;
 	if (pd->override_smi) {
 		if (pd->shared_smi != NULL)
@@ -2006,6 +2016,43 @@ static int mv643xx_eth_remove(struct pla
 	return 0;
 }
 
+static void mv643xx_eth_conf_mbus_windows(struct mv643xx_shared_private *msp,
+					  struct mbus_dram_target_info *dram)
+{
+	void __iomem *base = msp->eth_base;
+	u32 win_enable;
+	u32 win_protect;
+	int i;
+
+	for (i = 0; i < 6; i++) {
+		writel(0, base + WINDOW_BASE(i));
+		writel(0, base + WINDOW_SIZE(i));
+		if (i < 4)
+			writel(0, base + WINDOW_REMAP_HIGH(i));
+	}
+
+	win_enable = 0x3f;
+	win_protect = 0;
+
+	for (i = 0; i < dram->num_cs; i++) {
+		struct mbus_dram_window *cs = dram->cs + i;
+
+		writel((cs->base & 0xffff0000) |
+			 (cs->mbus_attr << 8) |
+			 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
+		writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
+
+		if (i < 4)
+			writel(0, base + WINDOW_REMAP_HIGH(i));
+
+		win_enable &= ~(1 << i);
+		win_protect |= 3 << (2 * i);
+	}
+
+	writel(win_enable, base + WINDOW_BAR_ENABLE);
+	msp->win_protect = win_protect;
+}
+
 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
 {
 	static int mv643xx_version_printed = 0;
@@ -2026,6 +2073,7 @@ static int mv643xx_eth_shared_probe(stru
 	msp = kmalloc(sizeof(*msp), GFP_KERNEL);
 	if (msp == NULL)
 		goto out;
+	memset(msp, 0, sizeof(*msp));
 
 	msp->eth_base = ioremap(res->start, res->end - res->start + 1);
 	if (msp->eth_base == NULL)
@@ -2036,6 +2084,12 @@ static int mv643xx_eth_shared_probe(stru
 
 	platform_set_drvdata(pdev, msp);
 
+	/*
+	 * (Re-)program MBUS remapping windows if we are asked to.
+	 */
+	if (pd != NULL && pd->dram != NULL)
+		mv643xx_eth_conf_mbus_windows(msp, pd->dram);
+
 	return 0;
 
 
Index: linux-2.6.25-rc4/include/linux/mv643xx_eth.h
===================================================================
--- linux-2.6.25-rc4.orig/include/linux/mv643xx_eth.h
+++ linux-2.6.25-rc4/include/linux/mv643xx_eth.h
@@ -5,6 +5,8 @@
 #ifndef __LINUX_MV643XX_ETH_H
 #define __LINUX_MV643XX_ETH_H
 
+#include <linux/mbus.h>
+
 #define MV643XX_ETH_SHARED_NAME		"mv643xx_eth_comm"
 #define MV643XX_ETH_NAME		"mv643xx_eth"
 #define MV643XX_ETH_SHARED_REGS		0x2000
@@ -15,6 +17,7 @@
 
 struct mv643xx_eth_shared_platform_data {
 	unsigned int	t_clk;
+	struct mbus_dram_target_info	*dram;
 };
 
 struct mv643xx_eth_platform_data {
--
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[PATCH 5/7] mv643xx_eth: mbus decode window support

[Lennert Buytenhek]

Make it possible to pass mbus_dram_target_info to the mv643xx_eth
driver via the platform data, and make the mv643xx_eth driver
program the window registers based on this data if it is passed in.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>

Index: linux-2.6.25-rc4/drivers/net/mv643xx_eth.c
===================================================================
--- linux-2.6.25-rc4.orig/drivers/net/mv643xx_eth.c
+++ linux-2.6.25-rc4/drivers/net/mv643xx_eth.c
@@ -91,6 +91,11 @@
  */
 #define PHY_ADDR_REG				0x0000
 #define SMI_REG					0x0004
+#define WINDOW_BASE(i)				(0x0200 + ((i) << 3))
+#define WINDOW_SIZE(i)				(0x0204 + ((i) << 3))
+#define WINDOW_REMAP_HIGH(i)			(0x0280 + ((i) << 2))
+#define WINDOW_BAR_ENABLE			0x0290
+#define WINDOW_PROTECT(i)			(0x0294 + ((i) << 4))
 
 /*
  * Per-port registers.
@@ -514,6 +519,8 @@ struct mv643xx_shared_private {
 	spinlock_t phy_lock;
 
 	unsigned int t_clk;
+
+	u32 win_protect;
 };
 
 struct mv643xx_private {
@@ -1892,6 +1899,9 @@ static int mv643xx_eth_probe(struct plat
 	mp->shared = platform_get_drvdata(pd->shared);
 	port_num = mp->port_num = pd->port_number;
 
+	if (mp->shared->win_protect)
+		wrl(mp, WINDOW_PROTECT(port_num), mp->shared->win_protect);
+
 	mp->shared_smi = mp->shared;
 	if (pd->override_smi) {
 		if (pd->shared_smi != NULL)
@@ -2006,6 +2016,43 @@ static int mv643xx_eth_remove(struct pla
 	return 0;
 }
 
+static void mv643xx_eth_conf_mbus_windows(struct mv643xx_shared_private *msp,
+					  struct mbus_dram_target_info *dram)
+{
+	void __iomem *base = msp->eth_base;
+	u32 win_enable;
+	u32 win_protect;
+	int i;
+
+	for (i = 0; i < 6; i++) {
+		writel(0, base + WINDOW_BASE(i));
+		writel(0, base + WINDOW_SIZE(i));
+		if (i < 4)
+			writel(0, base + WINDOW_REMAP_HIGH(i));
+	}
+
+	win_enable = 0x3f;
+	win_protect = 0;
+
+	for (i = 0; i < dram->num_cs; i++) {
+		struct mbus_dram_window *cs = dram->cs + i;
+
+		writel((cs->base & 0xffff0000) |
+			 (cs->mbus_attr << 8) |
+			 dram->mbus_dram_target_id, base + WINDOW_BASE(i));
+		writel((cs->size - 1) & 0xffff0000, base + WINDOW_SIZE(i));
+
+		if (i < 4)
+			writel(0, base + WINDOW_REMAP_HIGH(i));
+
+		win_enable &= ~(1 << i);
+		win_protect |= 3 << (2 * i);
+	}
+
+	writel(win_enable, base + WINDOW_BAR_ENABLE);
+	msp->win_protect = win_protect;
+}
+
 static int mv643xx_eth_shared_probe(struct platform_device *pdev)
 {
 	static int mv643xx_version_printed = 0;
@@ -2026,6 +2073,7 @@ static int mv643xx_eth_shared_probe(stru
 	msp = kmalloc(sizeof(*msp), GFP_KERNEL);
 	if (msp == NULL)
 		goto out;
+	memset(msp, 0, sizeof(*msp));
 
 	msp->eth_base = ioremap(res->start, res->end - res->start + 1);
 	if (msp->eth_base == NULL)
@@ -2036,6 +2084,12 @@ static int mv643xx_eth_shared_probe(stru
 
 	platform_set_drvdata(pdev, msp);
 
+	/*
+	 * (Re-)program MBUS remapping windows if we are asked to.
+	 */
+	if (pd != NULL && pd->dram != NULL)
+		mv643xx_eth_conf_mbus_windows(msp, pd->dram);
+
 	return 0;
 
 
Index: linux-2.6.25-rc4/include/linux/mv643xx_eth.h
===================================================================
--- linux-2.6.25-rc4.orig/include/linux/mv643xx_eth.h
+++ linux-2.6.25-rc4/include/linux/mv643xx_eth.h
@@ -5,6 +5,8 @@
 #ifndef __LINUX_MV643XX_ETH_H
 #define __LINUX_MV643XX_ETH_H
 
+#include <linux/mbus.h>
+
 #define MV643XX_ETH_SHARED_NAME		"mv643xx_eth_comm"
 #define MV643XX_ETH_NAME		"mv643xx_eth"
 #define MV643XX_ETH_SHARED_REGS		0x2000
@@ -15,6 +17,7 @@
 
 struct mv643xx_eth_shared_platform_data {
 	unsigned int	t_clk;
+	struct mbus_dram_target_info	*dram;
 };
 
 struct mv643xx_eth_platform_data {

[PATCH 6/7] sata_mv: mbus decode window support

[Lennert Buytenhek]

Make it possible to pass mbus_dram_target_info to the sata_mv
driver via the platform data, and make the sata_mv driver program
the window registers based on this data if it is passed in.

Signed-off-by: Lennert Buytenhek <buytenh-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>

Index: linux-2.6.25-rc4/drivers/ata/sata_mv.c
===================================================================
--- linux-2.6.25-rc4.orig/drivers/ata/sata_mv.c
+++ linux-2.6.25-rc4/drivers/ata/sata_mv.c
@@ -74,6 +74,7 @@
 #include <linux/device.h>
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
+#include <linux/mbus.h>
 #include <scsi/scsi_host.h>
 #include <scsi/scsi_cmnd.h>
 #include <scsi/scsi_device.h>
@@ -352,6 +353,9 @@ enum {
 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
 #define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC))
 
+#define WINDOW_CTRL(i)		(0x20030 + ((i) << 4))
+#define WINDOW_BASE(i)		(0x20034 + ((i) << 4))
+
 enum {
 	/* DMA boundary 0xffff is required by the s/g splitting
 	 * we need on /length/ in mv_fill-sg().
@@ -2897,6 +2901,27 @@ static int mv_create_dma_pools(struct mv
 	return 0;
 }
 
+static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
+				 struct mbus_dram_target_info *dram)
+{
+	int i;
+
+	for (i = 0; i < 4; i++) {
+		writel(0, hpriv->base + WINDOW_CTRL(i));
+		writel(0, hpriv->base + WINDOW_BASE(i));
+	}
+
+	for (i = 0; i < dram->num_cs; i++) {
+		struct mbus_dram_window *cs = dram->cs + i;
+
+		writel(((cs->size - 1) & 0xffff0000) |
+			(cs->mbus_attr << 8) |
+			(dram->mbus_dram_target_id << 4) | 1,
+			hpriv->base + WINDOW_CTRL(i));
+		writel(cs->base, hpriv->base + WINDOW_BASE(i));
+	}
+}
+
 /**
  *      mv_platform_probe - handle a positive probe of an soc Marvell
  *      host
@@ -2951,6 +2976,12 @@ static int mv_platform_probe(struct plat
 				   res->end - res->start + 1);
 	hpriv->base -= MV_SATAHC0_REG_BASE;
 
+	/*
+	 * (Re-)program MBUS remapping windows if we are asked to.
+	 */
+	if (mv_platform_data->dram != NULL)
+		mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
+
 	rc = mv_create_dma_pools(hpriv, &pdev->dev);
 	if (rc)
 		return rc;
Index: linux-2.6.25-rc4/include/linux/ata_platform.h
===================================================================
--- linux-2.6.25-rc4.orig/include/linux/ata_platform.h
+++ linux-2.6.25-rc4/include/linux/ata_platform.h
@@ -27,7 +27,10 @@ extern int __devexit __pata_platform_rem
 /*
  * Marvell SATA private data
  */
+struct mbus_dram_target_info;
+
 struct mv_sata_platform_data {
+	struct mbus_dram_target_info	*dram;
 	int	n_ports; /* number of sata ports */
 };
--
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[PATCH 6/7] sata_mv: mbus decode window support

[Lennert Buytenhek]

Make it possible to pass mbus_dram_target_info to the sata_mv
driver via the platform data, and make the sata_mv driver program
the window registers based on this data if it is passed in.

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>

Index: linux-2.6.25-rc4/drivers/ata/sata_mv.c
===================================================================
--- linux-2.6.25-rc4.orig/drivers/ata/sata_mv.c
+++ linux-2.6.25-rc4/drivers/ata/sata_mv.c
@@ -74,6 +74,7 @@
 #include <linux/device.h>
 #include <linux/platform_device.h>
 #include <linux/ata_platform.h>
+#include <linux/mbus.h>
 #include <scsi/scsi_host.h>
 #include <scsi/scsi_cmnd.h>
 #include <scsi/scsi_device.h>
@@ -352,6 +353,9 @@ enum {
 #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
 #define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC))
 
+#define WINDOW_CTRL(i)		(0x20030 + ((i) << 4))
+#define WINDOW_BASE(i)		(0x20034 + ((i) << 4))
+
 enum {
 	/* DMA boundary 0xffff is required by the s/g splitting
 	 * we need on /length/ in mv_fill-sg().
@@ -2897,6 +2901,27 @@ static int mv_create_dma_pools(struct mv
 	return 0;
 }
 
+static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
+				 struct mbus_dram_target_info *dram)
+{
+	int i;
+
+	for (i = 0; i < 4; i++) {
+		writel(0, hpriv->base + WINDOW_CTRL(i));
+		writel(0, hpriv->base + WINDOW_BASE(i));
+	}
+
+	for (i = 0; i < dram->num_cs; i++) {
+		struct mbus_dram_window *cs = dram->cs + i;
+
+		writel(((cs->size - 1) & 0xffff0000) |
+			(cs->mbus_attr << 8) |
+			(dram->mbus_dram_target_id << 4) | 1,
+			hpriv->base + WINDOW_CTRL(i));
+		writel(cs->base, hpriv->base + WINDOW_BASE(i));
+	}
+}
+
 /**
  *      mv_platform_probe - handle a positive probe of an soc Marvell
  *      host
@@ -2951,6 +2976,12 @@ static int mv_platform_probe(struct plat
 				   res->end - res->start + 1);
 	hpriv->base -= MV_SATAHC0_REG_BASE;
 
+	/*
+	 * (Re-)program MBUS remapping windows if we are asked to.
+	 */
+	if (mv_platform_data->dram != NULL)
+		mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
+
 	rc = mv_create_dma_pools(hpriv, &pdev->dev);
 	if (rc)
 		return rc;
Index: linux-2.6.25-rc4/include/linux/ata_platform.h
===================================================================
--- linux-2.6.25-rc4.orig/include/linux/ata_platform.h
+++ linux-2.6.25-rc4/include/linux/ata_platform.h
@@ -27,7 +27,10 @@ extern int __devexit __pata_platform_rem
 /*
  * Marvell SATA private data
  */
+struct mbus_dram_target_info;
+
 struct mv_sata_platform_data {
+	struct mbus_dram_target_info	*dram;
 	int	n_ports; /* number of sata ports */
 };

[PATCH 7/7] Orion: leave peripheral window programming up to drivers

[Lennert Buytenhek]

Pass in Orion's mbus_dram_info to the common instantiation of the
EHCI, ethernet and SATA peripherals, and remove the remaining
peripheral window setting code and assorted defines from Orion's
addr-map.c (leaving only the CPU outbound window setting code.)

Signed-off-by: Lennert Buytenhek <buytenh-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>

Index: linux-2.6.25-rc4/arch/arm/mach-orion/addr-map.c
===================================================================
--- linux-2.6.25-rc4.orig/arch/arm/mach-orion/addr-map.c
+++ linux-2.6.25-rc4/arch/arm/mach-orion/addr-map.c
@@ -34,11 +34,7 @@
  * Non-CPU Masters address decoding --
  * Unlike the CPU, we setup the access from Orion's master interfaces to DDR
  * banks only (the typical use case).
- * Setup access for each master to DDR is issued by common.c.
- *
- * Note: although orion_setbits() and orion_clrbits() are not atomic
- * no locking is necessary here since code in this file is only called
- * at boot time when there is no concurrency issues.
+ * Setup access for each master to DDR is issued by platform device setup.
  */
 
 /*
@@ -48,10 +44,6 @@
 #define TARGET_PCI		3
 #define TARGET_PCIE		4
 #define TARGET_DEV_BUS		1
-#define ATTR_DDR_CS(n)		(((n) ==0) ? 0xe :	\
-				((n) == 1) ? 0xd :	\
-				((n) == 2) ? 0xb :	\
-				((n) == 3) ? 0x7 : 0xf)
 #define ATTR_PCIE_MEM		0x59
 #define ATTR_PCIE_IO		0x51
 #define ATTR_PCIE_WA		0x79
@@ -61,17 +53,12 @@
 #define ATTR_DEV_CS1		0x1d
 #define ATTR_DEV_CS2		0x1b
 #define ATTR_DEV_BOOT		0xf
-#define WIN_EN			1
 
 /*
- * Helpers to get DDR banks info
+ * Helpers to get DDR bank info
  */
-#define DDR_BASE_CS(n)		ORION_DDR_REG(0x1500 + ((n) * 8))
-#define DDR_SIZE_CS(n)		ORION_DDR_REG(0x1504 + ((n) * 8))
-#define DDR_MAX_CS		4
-#define DDR_REG_TO_SIZE(reg)	(((reg) | 0xffffff) + 1)
-#define DDR_REG_TO_BASE(reg)	((reg) & 0xff000000)
-#define DDR_BANK_EN		1
+#define DDR_BASE_CS(n)		ORION_DDR_REG(0x1500 + ((n) << 3))
+#define DDR_SIZE_CS(n)		ORION_DDR_REG(0x1504 + ((n) << 3))
 
 /*
  * CPU Address Decode Windows registers
@@ -81,32 +68,6 @@
 #define CPU_WIN_REMAP_LO(n)	ORION_BRIDGE_REG(0x008 | ((n) << 4))
 #define CPU_WIN_REMAP_HI(n)	ORION_BRIDGE_REG(0x00c | ((n) << 4))
 
-/*
- * Gigabit Ethernet Address Decode Windows registers
- */
-#define ETH_WIN_BASE(win)	ORION_ETH_REG(0x200 + ((win) * 8))
-#define ETH_WIN_SIZE(win)	ORION_ETH_REG(0x204 + ((win) * 8))
-#define ETH_WIN_REMAP(win)	ORION_ETH_REG(0x280 + ((win) * 4))
-#define ETH_WIN_EN		ORION_ETH_REG(0x290)
-#define ETH_WIN_PROT		ORION_ETH_REG(0x294)
-#define ETH_MAX_WIN		6
-#define ETH_MAX_REMAP_WIN	4
-
-/*
- * USB Address Decode Windows registers
- */
-#define USB_WIN_CTRL(i, w)	((i == 0) ? ORION_USB0_REG(0x320 + ((w) << 4)) \
-					: ORION_USB1_REG(0x320 + ((w) << 4)))
-#define USB_WIN_BASE(i, w)	((i == 0) ? ORION_USB0_REG(0x324 + ((w) << 4)) \
-					: ORION_USB1_REG(0x324 + ((w) << 4)))
-#define USB_MAX_WIN		4
-
-/*
- * SATA Address Decode Windows registers
- */
-#define SATA_WIN_CTRL(win)	ORION_SATA_REG(0x30 + ((win) * 0x10))
-#define SATA_WIN_BASE(win)	ORION_SATA_REG(0x34 + ((win) * 0x10))
-#define SATA_MAX_WIN		4
 
 
 struct mbus_dram_target_info orion_mbus_dram_info;
@@ -218,112 +179,3 @@ void __init orion_setup_pcie_wa_win(u32 
 {
 	setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1);
 }
-
-
-void __init orion_setup_usb_wins(void)
-{
-	int i;
-	u32 usb_if, dev, rev;
-	u32 max_usb_if = 1;
-
-	orion_pcie_id(&dev, &rev);
-	if (dev == MV88F5182_DEV_ID)
-		max_usb_if = 2;
-
-	for (usb_if = 0; usb_if < max_usb_if; usb_if++) {
-		/*
-		 * First, disable and clear windows
-		 */
-		for (i = 0; i < USB_MAX_WIN; i++) {
-			orion_write(USB_WIN_BASE(usb_if, i), 0);
-			orion_write(USB_WIN_CTRL(usb_if, i), 0);
-		}
-
-		/*
-		 * Setup windows for DDR banks.
-		 */
-		for (i = 0; i < DDR_MAX_CS; i++) {
-			u32 base, size;
-			size = orion_read(DDR_SIZE_CS(i));
-			base = orion_read(DDR_BASE_CS(i));
-			if (size & DDR_BANK_EN) {
-				base = DDR_REG_TO_BASE(base);
-				size = DDR_REG_TO_SIZE(size);
-				orion_write(USB_WIN_CTRL(usb_if, i),
-						((size-1) & 0xffff0000) |
-						(ATTR_DDR_CS(i) << 8) |
-						(TARGET_DDR << 4) | WIN_EN);
-				orion_write(USB_WIN_BASE(usb_if, i),
-						base & 0xffff0000);
-			}
-		}
-	}
-}
-
-void __init orion_setup_eth_wins(void)
-{
-	int i;
-
-	/*
-	 * First, disable and clear windows
-	 */
-	for (i = 0; i < ETH_MAX_WIN; i++) {
-		orion_write(ETH_WIN_BASE(i), 0);
-		orion_write(ETH_WIN_SIZE(i), 0);
-		orion_setbits(ETH_WIN_EN, 1 << i);
-		orion_clrbits(ETH_WIN_PROT, 0x3 << (i * 2));
-		if (i < ETH_MAX_REMAP_WIN)
-			orion_write(ETH_WIN_REMAP(i), 0);
-	}
-
-	/*
-	 * Setup windows for DDR banks.
-	 */
-	for (i = 0; i < DDR_MAX_CS; i++) {
-		u32 base, size;
-		size = orion_read(DDR_SIZE_CS(i));
-		base = orion_read(DDR_BASE_CS(i));
-		if (size & DDR_BANK_EN) {
-			base = DDR_REG_TO_BASE(base);
-			size = DDR_REG_TO_SIZE(size);
-			orion_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000);
-			orion_write(ETH_WIN_BASE(i), (base & 0xffff0000) |
-					(ATTR_DDR_CS(i) << 8) |
-					TARGET_DDR);
-			orion_clrbits(ETH_WIN_EN, 1 << i);
-			orion_setbits(ETH_WIN_PROT, 0x3 << (i * 2));
-		}
-	}
-}
-
-void __init orion_setup_sata_wins(void)
-{
-	int i;
-
-	/*
-	 * First, disable and clear windows
-	 */
-	for (i = 0; i < SATA_MAX_WIN; i++) {
-		orion_write(SATA_WIN_BASE(i), 0);
-		orion_write(SATA_WIN_CTRL(i), 0);
-	}
-
-	/*
-	 * Setup windows for DDR banks.
-	 */
-	for (i = 0; i < DDR_MAX_CS; i++) {
-		u32 base, size;
-		size = orion_read(DDR_SIZE_CS(i));
-		base = orion_read(DDR_BASE_CS(i));
-		if (size & DDR_BANK_EN) {
-			base = DDR_REG_TO_BASE(base);
-			size = DDR_REG_TO_SIZE(size);
-			orion_write(SATA_WIN_CTRL(i),
-					((size-1) & 0xffff0000) |
-					(ATTR_DDR_CS(i) << 8) |
-					(TARGET_DDR << 4) | WIN_EN);
-			orion_write(SATA_WIN_BASE(i),
-					base & 0xffff0000);
-		}
-	}
-}
Index: linux-2.6.25-rc4/arch/arm/mach-orion/common.c
===================================================================
--- linux-2.6.25-rc4.orig/arch/arm/mach-orion/common.c
+++ linux-2.6.25-rc4/arch/arm/mach-orion/common.c
@@ -14,12 +14,15 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
+#include <linux/mbus.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/mv643xx_i2c.h>
+#include <linux/ata_platform.h>
 #include <asm/page.h>
 #include <asm/timex.h>
 #include <asm/mach/map.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/platform.h>
 #include "common.h"
 
 /*****************************************************************************
@@ -146,6 +149,10 @@ static struct resource orion_ehci1_resou
 	},
 };
 
+static struct orion_ehci_data orion_ehci_data = {
+	.dram		= &orion_mbus_dram_info,
+};
+
 static u64 ehci_dmamask = 0xffffffffUL;
 
 static struct platform_device orion_ehci0 = {
@@ -154,6 +161,7 @@ static struct platform_device orion_ehci
 	.dev		= {
 		.dma_mask		= &ehci_dmamask,
 		.coherent_dma_mask	= 0xffffffff,
+		.platform_data		= &orion_ehci_data,
 	},
 	.resource	= orion_ehci0_resources,
 	.num_resources	= ARRAY_SIZE(orion_ehci0_resources),
@@ -165,6 +173,7 @@ static struct platform_device orion_ehci
 	.dev		= {
 		.dma_mask		= &ehci_dmamask,
 		.coherent_dma_mask	= 0xffffffff,
+		.platform_data		= &orion_ehci_data,
 	},
 	.resource	= orion_ehci1_resources,
 	.num_resources	= ARRAY_SIZE(orion_ehci1_resources),
@@ -185,6 +194,7 @@ static struct resource orion_eth_shared_
 
 struct mv643xx_eth_shared_platform_data orion_eth_shared_data = {
 	.t_clk		= ORION_TCLK,
+	.dram		= &orion_mbus_dram_info,
 };
 
 static struct platform_device orion_eth_shared = {
@@ -288,6 +298,7 @@ static struct platform_device orion_sata
 
 void __init orion_sata_init(struct mv_sata_platform_data *sata_data)
 {
+	sata_data->dram = &orion_mbus_dram_info;
 	orion_sata.dev.platform_data = sata_data;
 	platform_device_register(&orion_sata);
 }
@@ -340,10 +351,6 @@ void __init orion_init(void)
 	 * Setup Orion address map
 	 */
 	orion_setup_cpu_mbus_bridge();
-	orion_setup_usb_wins();
-	orion_setup_eth_wins();
-	if (dev == MV88F5182_DEV_ID)
-		orion_setup_sata_wins();
 
 	/*
 	 * REgister devices
Index: linux-2.6.25-rc4/arch/arm/mach-orion/common.h
===================================================================
--- linux-2.6.25-rc4.orig/arch/arm/mach-orion/common.h
+++ linux-2.6.25-rc4/arch/arm/mach-orion/common.h
@@ -21,9 +21,6 @@ void orion_setup_dev0_win(u32 base, u32 
 void orion_setup_dev1_win(u32 base, u32 size);
 void orion_setup_dev2_win(u32 base, u32 size);
 void orion_setup_pcie_wa_win(u32 base, u32 size);
-void orion_setup_eth_wins(void);
-void orion_setup_usb_wins(void);
-void orion_setup_sata_wins(void);
 
 /*
  * Shared code used internally by other Orion core functions.
--
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[PATCH 7/7] Orion: leave peripheral window programming up to drivers

[Lennert Buytenhek]

Pass in Orion's mbus_dram_info to the common instantiation of the
EHCI, ethernet and SATA peripherals, and remove the remaining
peripheral window setting code and assorted defines from Orion's
addr-map.c (leaving only the CPU outbound window setting code.)

Signed-off-by: Lennert Buytenhek <buytenh@marvell.com>

Index: linux-2.6.25-rc4/arch/arm/mach-orion/addr-map.c
===================================================================
--- linux-2.6.25-rc4.orig/arch/arm/mach-orion/addr-map.c
+++ linux-2.6.25-rc4/arch/arm/mach-orion/addr-map.c
@@ -34,11 +34,7 @@
  * Non-CPU Masters address decoding --
  * Unlike the CPU, we setup the access from Orion's master interfaces to DDR
  * banks only (the typical use case).
- * Setup access for each master to DDR is issued by common.c.
- *
- * Note: although orion_setbits() and orion_clrbits() are not atomic
- * no locking is necessary here since code in this file is only called
- * at boot time when there is no concurrency issues.
+ * Setup access for each master to DDR is issued by platform device setup.
  */
 
 /*
@@ -48,10 +44,6 @@
 #define TARGET_PCI		3
 #define TARGET_PCIE		4
 #define TARGET_DEV_BUS		1
-#define ATTR_DDR_CS(n)		(((n) ==0) ? 0xe :	\
-				((n) == 1) ? 0xd :	\
-				((n) == 2) ? 0xb :	\
-				((n) == 3) ? 0x7 : 0xf)
 #define ATTR_PCIE_MEM		0x59
 #define ATTR_PCIE_IO		0x51
 #define ATTR_PCIE_WA		0x79
@@ -61,17 +53,12 @@
 #define ATTR_DEV_CS1		0x1d
 #define ATTR_DEV_CS2		0x1b
 #define ATTR_DEV_BOOT		0xf
-#define WIN_EN			1
 
 /*
- * Helpers to get DDR banks info
+ * Helpers to get DDR bank info
  */
-#define DDR_BASE_CS(n)		ORION_DDR_REG(0x1500 + ((n) * 8))
-#define DDR_SIZE_CS(n)		ORION_DDR_REG(0x1504 + ((n) * 8))
-#define DDR_MAX_CS		4
-#define DDR_REG_TO_SIZE(reg)	(((reg) | 0xffffff) + 1)
-#define DDR_REG_TO_BASE(reg)	((reg) & 0xff000000)
-#define DDR_BANK_EN		1
+#define DDR_BASE_CS(n)		ORION_DDR_REG(0x1500 + ((n) << 3))
+#define DDR_SIZE_CS(n)		ORION_DDR_REG(0x1504 + ((n) << 3))
 
 /*
  * CPU Address Decode Windows registers
@@ -81,32 +68,6 @@
 #define CPU_WIN_REMAP_LO(n)	ORION_BRIDGE_REG(0x008 | ((n) << 4))
 #define CPU_WIN_REMAP_HI(n)	ORION_BRIDGE_REG(0x00c | ((n) << 4))
 
-/*
- * Gigabit Ethernet Address Decode Windows registers
- */
-#define ETH_WIN_BASE(win)	ORION_ETH_REG(0x200 + ((win) * 8))
-#define ETH_WIN_SIZE(win)	ORION_ETH_REG(0x204 + ((win) * 8))
-#define ETH_WIN_REMAP(win)	ORION_ETH_REG(0x280 + ((win) * 4))
-#define ETH_WIN_EN		ORION_ETH_REG(0x290)
-#define ETH_WIN_PROT		ORION_ETH_REG(0x294)
-#define ETH_MAX_WIN		6
-#define ETH_MAX_REMAP_WIN	4
-
-/*
- * USB Address Decode Windows registers
- */
-#define USB_WIN_CTRL(i, w)	((i == 0) ? ORION_USB0_REG(0x320 + ((w) << 4)) \
-					: ORION_USB1_REG(0x320 + ((w) << 4)))
-#define USB_WIN_BASE(i, w)	((i == 0) ? ORION_USB0_REG(0x324 + ((w) << 4)) \
-					: ORION_USB1_REG(0x324 + ((w) << 4)))
-#define USB_MAX_WIN		4
-
-/*
- * SATA Address Decode Windows registers
- */
-#define SATA_WIN_CTRL(win)	ORION_SATA_REG(0x30 + ((win) * 0x10))
-#define SATA_WIN_BASE(win)	ORION_SATA_REG(0x34 + ((win) * 0x10))
-#define SATA_MAX_WIN		4
 
 
 struct mbus_dram_target_info orion_mbus_dram_info;
@@ -218,112 +179,3 @@ void __init orion_setup_pcie_wa_win(u32 
 {
 	setup_cpu_win(7, base, size, TARGET_PCIE, ATTR_PCIE_WA, -1);
 }
-
-
-void __init orion_setup_usb_wins(void)
-{
-	int i;
-	u32 usb_if, dev, rev;
-	u32 max_usb_if = 1;
-
-	orion_pcie_id(&dev, &rev);
-	if (dev == MV88F5182_DEV_ID)
-		max_usb_if = 2;
-
-	for (usb_if = 0; usb_if < max_usb_if; usb_if++) {
-		/*
-		 * First, disable and clear windows
-		 */
-		for (i = 0; i < USB_MAX_WIN; i++) {
-			orion_write(USB_WIN_BASE(usb_if, i), 0);
-			orion_write(USB_WIN_CTRL(usb_if, i), 0);
-		}
-
-		/*
-		 * Setup windows for DDR banks.
-		 */
-		for (i = 0; i < DDR_MAX_CS; i++) {
-			u32 base, size;
-			size = orion_read(DDR_SIZE_CS(i));
-			base = orion_read(DDR_BASE_CS(i));
-			if (size & DDR_BANK_EN) {
-				base = DDR_REG_TO_BASE(base);
-				size = DDR_REG_TO_SIZE(size);
-				orion_write(USB_WIN_CTRL(usb_if, i),
-						((size-1) & 0xffff0000) |
-						(ATTR_DDR_CS(i) << 8) |
-						(TARGET_DDR << 4) | WIN_EN);
-				orion_write(USB_WIN_BASE(usb_if, i),
-						base & 0xffff0000);
-			}
-		}
-	}
-}
-
-void __init orion_setup_eth_wins(void)
-{
-	int i;
-
-	/*
-	 * First, disable and clear windows
-	 */
-	for (i = 0; i < ETH_MAX_WIN; i++) {
-		orion_write(ETH_WIN_BASE(i), 0);
-		orion_write(ETH_WIN_SIZE(i), 0);
-		orion_setbits(ETH_WIN_EN, 1 << i);
-		orion_clrbits(ETH_WIN_PROT, 0x3 << (i * 2));
-		if (i < ETH_MAX_REMAP_WIN)
-			orion_write(ETH_WIN_REMAP(i), 0);
-	}
-
-	/*
-	 * Setup windows for DDR banks.
-	 */
-	for (i = 0; i < DDR_MAX_CS; i++) {
-		u32 base, size;
-		size = orion_read(DDR_SIZE_CS(i));
-		base = orion_read(DDR_BASE_CS(i));
-		if (size & DDR_BANK_EN) {
-			base = DDR_REG_TO_BASE(base);
-			size = DDR_REG_TO_SIZE(size);
-			orion_write(ETH_WIN_SIZE(i), (size-1) & 0xffff0000);
-			orion_write(ETH_WIN_BASE(i), (base & 0xffff0000) |
-					(ATTR_DDR_CS(i) << 8) |
-					TARGET_DDR);
-			orion_clrbits(ETH_WIN_EN, 1 << i);
-			orion_setbits(ETH_WIN_PROT, 0x3 << (i * 2));
-		}
-	}
-}
-
-void __init orion_setup_sata_wins(void)
-{
-	int i;
-
-	/*
-	 * First, disable and clear windows
-	 */
-	for (i = 0; i < SATA_MAX_WIN; i++) {
-		orion_write(SATA_WIN_BASE(i), 0);
-		orion_write(SATA_WIN_CTRL(i), 0);
-	}
-
-	/*
-	 * Setup windows for DDR banks.
-	 */
-	for (i = 0; i < DDR_MAX_CS; i++) {
-		u32 base, size;
-		size = orion_read(DDR_SIZE_CS(i));
-		base = orion_read(DDR_BASE_CS(i));
-		if (size & DDR_BANK_EN) {
-			base = DDR_REG_TO_BASE(base);
-			size = DDR_REG_TO_SIZE(size);
-			orion_write(SATA_WIN_CTRL(i),
-					((size-1) & 0xffff0000) |
-					(ATTR_DDR_CS(i) << 8) |
-					(TARGET_DDR << 4) | WIN_EN);
-			orion_write(SATA_WIN_BASE(i),
-					base & 0xffff0000);
-		}
-	}
-}
Index: linux-2.6.25-rc4/arch/arm/mach-orion/common.c
===================================================================
--- linux-2.6.25-rc4.orig/arch/arm/mach-orion/common.c
+++ linux-2.6.25-rc4/arch/arm/mach-orion/common.c
@@ -14,12 +14,15 @@
 #include <linux/init.h>
 #include <linux/platform_device.h>
 #include <linux/serial_8250.h>
+#include <linux/mbus.h>
 #include <linux/mv643xx_eth.h>
 #include <linux/mv643xx_i2c.h>
+#include <linux/ata_platform.h>
 #include <asm/page.h>
 #include <asm/timex.h>
 #include <asm/mach/map.h>
 #include <asm/arch/hardware.h>
+#include <asm/arch/platform.h>
 #include "common.h"
 
 /*****************************************************************************
@@ -146,6 +149,10 @@ static struct resource orion_ehci1_resou
 	},
 };
 
+static struct orion_ehci_data orion_ehci_data = {
+	.dram		= &orion_mbus_dram_info,
+};
+
 static u64 ehci_dmamask = 0xffffffffUL;
 
 static struct platform_device orion_ehci0 = {
@@ -154,6 +161,7 @@ static struct platform_device orion_ehci
 	.dev		= {
 		.dma_mask		= &ehci_dmamask,
 		.coherent_dma_mask	= 0xffffffff,
+		.platform_data		= &orion_ehci_data,
 	},
 	.resource	= orion_ehci0_resources,
 	.num_resources	= ARRAY_SIZE(orion_ehci0_resources),
@@ -165,6 +173,7 @@ static struct platform_device orion_ehci
 	.dev		= {
 		.dma_mask		= &ehci_dmamask,
 		.coherent_dma_mask	= 0xffffffff,
+		.platform_data		= &orion_ehci_data,
 	},
 	.resource	= orion_ehci1_resources,
 	.num_resources	= ARRAY_SIZE(orion_ehci1_resources),
@@ -185,6 +194,7 @@ static struct resource orion_eth_shared_
 
 struct mv643xx_eth_shared_platform_data orion_eth_shared_data = {
 	.t_clk		= ORION_TCLK,
+	.dram		= &orion_mbus_dram_info,
 };
 
 static struct platform_device orion_eth_shared = {
@@ -288,6 +298,7 @@ static struct platform_device orion_sata
 
 void __init orion_sata_init(struct mv_sata_platform_data *sata_data)
 {
+	sata_data->dram = &orion_mbus_dram_info;
 	orion_sata.dev.platform_data = sata_data;
 	platform_device_register(&orion_sata);
 }
@@ -340,10 +351,6 @@ void __init orion_init(void)
 	 * Setup Orion address map
 	 */
 	orion_setup_cpu_mbus_bridge();
-	orion_setup_usb_wins();
-	orion_setup_eth_wins();
-	if (dev == MV88F5182_DEV_ID)
-		orion_setup_sata_wins();
 
 	/*
 	 * REgister devices
Index: linux-2.6.25-rc4/arch/arm/mach-orion/common.h
===================================================================
--- linux-2.6.25-rc4.orig/arch/arm/mach-orion/common.h
+++ linux-2.6.25-rc4/arch/arm/mach-orion/common.h
@@ -21,9 +21,6 @@ void orion_setup_dev0_win(u32 base, u32 
 void orion_setup_dev1_win(u32 base, u32 size);
 void orion_setup_dev2_win(u32 base, u32 size);
 void orion_setup_pcie_wa_win(u32 base, u32 size);
-void orion_setup_eth_wins(void);
-void orion_setup_usb_wins(void);
-void orion_setup_sata_wins(void);
 
 /*
  * Shared code used internally by other Orion core functions.

Re: [PATCH 0/7][RFC] Move Marvell MBUS window handling into drivers

[Tzachi Perelstein]

Lennert Buytenhek wrote:
> 
> This patch set is an initial attempt at moving programming of the
> MBUS register windows for the set of MBUS peripherals that we currently
> have in-tree drivers for from platform code into drivers.
> 
> With these patches, info about DRAM target/attribute IDs is prepared
> by the platform code as usual, but then passed into platform drivers
> via platform device data, instead of programming that data into the
> peripherals directly.
> 
> This avoids duplicating the window programming code across each
> platform that wants to use these peripherals, and avoids exposing
> internal peripheral register set details outside of their drivers.
> 
> Comments appreciated.
> 

At the beginning I had some hard time to agree with this concept 
of leaving the mbus windows to be handled at drivers level instead 
of the arch level, mainly because the mbus bits looks somehow 
different on every orion/discovery chips. My feeling was that this 
approach will either fail on some chips or will be very cumbersome.

Well, I was wrong. Reviewing the patches against orion/discovery 
specs shows that this patchset indeed handles all these bits 
differences correctly, and in a very simple and elegant manner. 
So I like it a lot ;) 

For the whole set --
Reviewed-by: Tzachi Perelstein <tzachi-eYqpPyKDWXRBDgjK7y7TUQ@public.gmane.org>

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Re: [PATCH 0/7][RFC] Move Marvell MBUS window handling into drivers

[Tzachi Perelstein]

Lennert Buytenhek wrote:
> 
> This patch set is an initial attempt at moving programming of the
> MBUS register windows for the set of MBUS peripherals that we currently
> have in-tree drivers for from platform code into drivers.
> 
> With these patches, info about DRAM target/attribute IDs is prepared
> by the platform code as usual, but then passed into platform drivers
> via platform device data, instead of programming that data into the
> peripherals directly.
> 
> This avoids duplicating the window programming code across each
> platform that wants to use these peripherals, and avoids exposing
> internal peripheral register set details outside of their drivers.
> 
> Comments appreciated.
> 

At the beginning I had some hard time to agree with this concept 
of leaving the mbus windows to be handled at drivers level instead 
of the arch level, mainly because the mbus bits looks somehow 
different on every orion/discovery chips. My feeling was that this 
approach will either fail on some chips or will be very cumbersome.

Well, I was wrong. Reviewing the patches against orion/discovery 
specs shows that this patchset indeed handles all these bits 
differences correctly, and in a very simple and elegant manner. 
So I like it a lot ;) 

For the whole set --
Reviewed-by: Tzachi Perelstein <tzachi@marvell.com>

Re: [PATCH 0/7][RFC] Move Marvell MBUS window handling into drivers

[Russell King - ARM Linux]

On Fri, Mar 07, 2008 at 11:19:13AM +0100, Lennert Buytenhek wrote:
> Comments appreciated.

I have no issues with this approach.  Looks fine to me.
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Re: [PATCH 0/7][RFC] Move Marvell MBUS window handling into drivers

[Russell King - ARM Linux]

On Fri, Mar 07, 2008 at 11:19:13AM +0100, Lennert Buytenhek wrote:
> Comments appreciated.

I have no issues with this approach.  Looks fine to me.