From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Chris Friesen" Subject: Re: MMIO and gcc re-ordering issue Date: Tue, 27 May 2008 15:23:51 -0600 Message-ID: <483C7BE7.10204@nortel.com> References: <1211852026.3286.36.camel@pasglop> <20080526.184047.88207142.davem@davemloft.net> <1211854540.3286.42.camel@pasglop> <20080526.192812.184590464.davem@davemloft.net> <20080526204233.75b71bb8@infradead.org> <1211872130.3286.64.camel@pasglop> <1211906268.3435.44.camel@localhost.localdomain> <1211910825.7160.1.camel@localhost.localdomain> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: Sender: linux-kernel-owner@vger.kernel.org To: Roland Dreier Cc: James Bottomley , linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, David Miller , linuxppc-dev@ozlabs.org, scottwood@freescale.com, torvalds@linux-foundation.org, tpiepho@freescale.com, alan@lxorguk.ukuu.org.uk, Arjan van de Ven List-Id: linux-arch.vger.kernel.org Roland Dreier wrote: > Writes are posted yes, but not reordered arbitrarily. If I have code like: > > spin_lock(&mmio_lock); > writel(val1, reg1); > writel(val2, reg2); > spin_unlock(&mmio_lock); > > then I have a reasonable expectation that if two CPUs run this at the > same time, their writes to reg1/reg2 won't be interleaved with each > other (because the whole section is inside a spinlock). And Altix > violates that expectation. Does that necessarily follow? If you've got a large system with multiple pci bridges, could you end up with posted writes coming from different cpus taking a different amount of time to propagate to a device and thus colliding? Chris From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from zrtps0kp.nortel.com ([47.140.192.56]:40494 "EHLO zrtps0kp.nortel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1755811AbYE0WJz (ORCPT ); Tue, 27 May 2008 18:09:55 -0400 Message-ID: <483C7BE7.10204@nortel.com> Date: Tue, 27 May 2008 15:23:51 -0600 From: "Chris Friesen" MIME-Version: 1.0 Subject: Re: MMIO and gcc re-ordering issue References: <1211852026.3286.36.camel@pasglop> <20080526.184047.88207142.davem@davemloft.net> <1211854540.3286.42.camel@pasglop> <20080526.192812.184590464.davem@davemloft.net> <20080526204233.75b71bb8@infradead.org> <1211872130.3286.64.camel@pasglop> <1211906268.3435.44.camel@localhost.localdomain> <1211910825.7160.1.camel@localhost.localdomain> In-Reply-To: Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-arch-owner@vger.kernel.org List-ID: To: Roland Dreier Cc: James Bottomley , linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, David Miller , linuxppc-dev@ozlabs.org, scottwood@freescale.com, torvalds@linux-foundation.org, tpiepho@freescale.com, alan@lxorguk.ukuu.org.uk, Arjan van de Ven Message-ID: <20080527212351.2Nun-OKD5nkauKdsLeH4daG1fJeb6tf0HgK43x_wy0g@z> Roland Dreier wrote: > Writes are posted yes, but not reordered arbitrarily. If I have code like: > > spin_lock(&mmio_lock); > writel(val1, reg1); > writel(val2, reg2); > spin_unlock(&mmio_lock); > > then I have a reasonable expectation that if two CPUs run this at the > same time, their writes to reg1/reg2 won't be interleaved with each > other (because the whole section is inside a spinlock). And Altix > violates that expectation. Does that necessarily follow? If you've got a large system with multiple pci bridges, could you end up with posted writes coming from different cpus taking a different amount of time to propagate to a device and thus colliding? Chris