From mboxrd@z Thu Jan 1 00:00:00 1970 From: Avi Kivity Subject: Re: [PATCH 1/3] X86: Optimise fls(), ffs() and fls64() Date: Thu, 15 Apr 2010 11:49:56 +0300 Message-ID: <4BC6D334.8050607@redhat.com> References: <4BC5D19A.8000605@redhat.com> <20100406133026.GD20577@parisc-linux.org> <20100326144241.8583.95617.stgit@warthog.procyon.org.uk> <28287.1269625325@redhat.com> <20100326175827.GD20055@linux-mips.org> <17213.1271245760@redhat.com> <3879.1271321292@redhat.com> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1; format=flowed Content-Transfer-Encoding: 7bit Return-path: Received: from mx1.redhat.com ([209.132.183.28]:62805 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1757513Ab0DOIuV (ORCPT ); Thu, 15 Apr 2010 04:50:21 -0400 In-Reply-To: <3879.1271321292@redhat.com> Sender: linux-arch-owner@vger.kernel.org List-ID: To: David Howells Cc: Linus Torvalds , Matthew Wilcox , Ralf Baechle , mingo@elte.hu, tglx@linutronix.de, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org On 04/15/2010 11:48 AM, David Howells wrote: > Avi Kivity wrote: > > >> Even if Intel processors behave that way, other processors (real and >> emulated) use those manuals as a specification. Emulated processors are >> unlikely to touch an undefined register, but real processors may. >> >> (qemu tcg appears not to touch the output) >> > Possibly because the AMD64 spec specifies that the destination will be > unchanged if the source was 0. > Likely. But we haven't tested all current and future x86 clones, and they may be based off the Intel documentation instead of the AMD documentation. -- I have a truly marvellous patch that fixes the bug which this signature is too narrow to contain.