From: "H. Peter Anvin" <hpa@zytor.com>
To: Sam Ravnborg <sam@ravnborg.org>
Cc: Tejun Heo <tj@kernel.org>, Shaohua Li <shaohua.li@intel.com>,
lkml <linux-kernel@vger.kernel.org>,
Andrew Morton <akpm@linux-foundation.org>,
eric.dumazet@gmail.com, linux-arch@vger.kernel.org
Subject: Re: [PATCH RESEND percpu#for-next] percpu: align percpu readmostly subsection to cacheline
Date: Mon, 27 Dec 2010 13:03:53 -0800 [thread overview]
Message-ID: <4D18FF39.6080101@zytor.com> (raw)
In-Reply-To: <20101227204309.GA3878@merkur.ravnborg.org>
On 12/27/2010 12:43 PM, Sam Ravnborg wrote:
>
> It would have been better to include cache.h and then use L1_CACHE_BYTES,
> as the value differs for EV4.
> It will work with 64 as this is the bigger of the two.
>
> It looks like we could do this for almost all archs.
> But then I am not sure if "L1_CACHE_BYTES" is the same as
> a cacheline on the different archs.
>
For x86, L1 is definitely not the right cache line to use, in terms of
what matters for SMP sharing. And yes, there are x86's with smaller L1
than L2/3 cache line size.
-hpa
next prev parent reply other threads:[~2010-12-27 21:06 UTC|newest]
Thread overview: 13+ messages / expand[flat|nested] mbox.gz Atom feed top
2010-12-27 13:37 [PATCH RESEND percpu#for-next] percpu: align percpu readmostly subsection to cacheline Tejun Heo
2010-12-27 13:37 ` Tejun Heo
2010-12-27 20:17 ` H. Peter Anvin
2010-12-27 20:43 ` Sam Ravnborg
2010-12-27 20:43 ` Sam Ravnborg
2010-12-27 21:03 ` H. Peter Anvin [this message]
2010-12-28 11:18 ` Tejun Heo
2010-12-28 11:33 ` [PATCH] alpha: use L1_CACHE_BYTES for cacheline size in the linker script Tejun Heo
2011-01-25 13:28 ` Tejun Heo
2010-12-28 0:48 ` [PATCH RESEND percpu#for-next] percpu: align percpu readmostly subsection to cacheline Shaohua Li
2010-12-28 0:48 ` Shaohua Li
2011-01-25 13:32 ` Tejun Heo
2011-01-25 13:32 ` Tejun Heo
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