From mboxrd@z Thu Jan 1 00:00:00 1970 From: "H. Peter Anvin" Subject: Re: [PATCH RESEND percpu#for-next] percpu: align percpu readmostly subsection to cacheline Date: Mon, 27 Dec 2010 13:03:53 -0800 Message-ID: <4D18FF39.6080101@zytor.com> References: <20101227133719.GD488@htj.dyndns.org> <20101227204309.GA3878@merkur.ravnborg.org> Mime-Version: 1.0 Content-Type: text/plain; charset=ISO-8859-1 Content-Transfer-Encoding: 7bit Return-path: Received: from terminus.zytor.com ([198.137.202.10]:54010 "EHLO mail.zytor.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751007Ab0L0VGB (ORCPT ); Mon, 27 Dec 2010 16:06:01 -0500 In-Reply-To: <20101227204309.GA3878@merkur.ravnborg.org> Sender: linux-arch-owner@vger.kernel.org List-ID: To: Sam Ravnborg Cc: Tejun Heo , Shaohua Li , lkml , Andrew Morton , eric.dumazet@gmail.com, linux-arch@vger.kernel.org On 12/27/2010 12:43 PM, Sam Ravnborg wrote: > > It would have been better to include cache.h and then use L1_CACHE_BYTES, > as the value differs for EV4. > It will work with 64 as this is the bigger of the two. > > It looks like we could do this for almost all archs. > But then I am not sure if "L1_CACHE_BYTES" is the same as > a cacheline on the different archs. > For x86, L1 is definitely not the right cache line to use, in terms of what matters for SMP sharing. And yes, there are x86's with smaller L1 than L2/3 cache line size. -hpa