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Mon, 13 Apr 2026 02:18:11 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: linux-arch@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-ThreadId: Ab9VcpOYxc8o Date: Mon, 13 Apr 2026 08:17:50 +0200 From: "Arnd Bergmann" To: guoren , "Paul Walmsley" , "Palmer Dabbelt" , "Alexandre Ghiti" , "Leonardo Bras" , djordje.todorovic@htecgroup.com, aleksa.paunovic@htecgroup.com, "Han Gao" Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Linux-Arch , "Alexandre Ghiti" , "Han Gao" , "Yao Zi" , "Chen Wang" , "Inochi Amaoto" , "Xiaoguang Xing" , "Paul Walmsley" Message-Id: <535f3eaa-ff93-4de4-86c7-8a6e46bcca63@app.fastmail.com> In-Reply-To: <20260412143116.1445893-1-guoren@kernel.org> References: <20260412143116.1445893-1-guoren@kernel.org> Subject: Re: [PATCH V4] riscv: errata: Add ERRATA_THEAD_WRITE_ONCE fixup Content-Type: text/plain Content-Transfer-Encoding: 7bit On Sun, Apr 12, 2026, at 16:31, guoren@kernel.org wrote: > arch/riscv/Kconfig.errata | 17 ++++++++++ > arch/riscv/errata/thead/errata.c | 20 ++++++++++++ > arch/riscv/include/asm/errata_list_vendors.h | 3 +- > arch/riscv/include/asm/rwonce.h | 34 ++++++++++++++++++++ > include/asm-generic/rwonce.h | 2 ++ For asm-generic: Acked-by: Arnd Bergmann > +static bool errata_probe_write_once(unsigned int stage, > + unsigned long arch_id, unsigned long impid) > +{ > + if (!IS_ENABLED(CONFIG_ERRATA_THEAD_WRITE_ONCE)) > + return false; > + > + /* target-c9xx cores report arch_id and impid as 0 */ > + if (arch_id != 0 || impid != 0) > + return false; > + > + if (stage == RISCV_ALTERNATIVES_BOOT || > + stage == RISCV_ALTERNATIVES_MODULE) > + return true; Question: Are the affected cores the only ones that report arch_id==impid==0? If there are other known implementations that get the extra barrier but don't need it here, that should probably be mentioned in the Kconfig text and the code comment. Arnd