From mboxrd@z Thu Jan 1 00:00:00 1970 From: Peter Hurley Subject: Re: bit fields && data tearing Date: Fri, 05 Sep 2014 16:01:35 -0400 Message-ID: <540A169F.40906@hurleysoftware.com> References: <54079B70.4050200@hurleysoftware.com> <1409785893.30640.118.camel@pasglop> <063D6719AE5E284EB5DD2968C1650D6D17487172@AcuExch.aculab.com> <1409824374.4246.62.camel@pasglop> <5408E458.3@zytor.com> <54090AF4.7060406@hurleysoftware.com> <54091B30.2090509@zytor.com> <20140905081648.GB5281@omega> <20140905180950.GU5001@linux.vnet.ibm.com> <20140905183109.GA5497@linux.vnet.ibm.com> <20140905195234.GT4783@worktop.ger.corp.intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20140905195234.GT4783@worktop.ger.corp.intel.com> Sender: linux-ia64-owner@vger.kernel.org To: Peter Zijlstra , "Paul E. McKenney" Cc: Michael Cree , "H. Peter Anvin" , Benjamin Herrenschmidt , David Laight , Jakub Jelinek , "linux-arch@vger.kernel.org" , Tony Luck , "linux-ia64@vger.kernel.org" , Oleg Nesterov , "linux-kernel@vger.kernel.org" , Paul Mackerras , "linuxppc-dev@lists.ozlabs.org" , Miroslav Franc , Richard Henderson , linux-alpha@vger.kernel.org List-Id: linux-arch.vger.kernel.org On 09/05/2014 03:52 PM, Peter Zijlstra wrote: > On Fri, Sep 05, 2014 at 11:31:09AM -0700, Paul E. McKenney wrote: >> compiler: Allow 1- and 2-byte smp_load_acquire() and smp_store_release() >> >> CPUs without single-byte and double-byte loads and stores place some >> "interesting" requirements on concurrent code. For example (adapted >> from Peter Hurley's test code), suppose we have the following structure: >> >> struct foo { >> spinlock_t lock1; >> spinlock_t lock2; >> char a; /* Protected by lock1. */ >> char b; /* Protected by lock2. */ >> }; >> struct foo *foop; >> >> Of course, it is common (and good) practice to place data protected >> by different locks in separate cache lines. However, if the locks are >> rarely acquired (for example, only in rare error cases), and there are >> a great many instances of the data structure, then memory footprint can >> trump false-sharing concerns, so that it can be better to place them in >> the same cache cache line as above. >> >> But if the CPU does not support single-byte loads and stores, a store >> to foop->a will do a non-atomic read-modify-write operation on foop->b, >> which will come as a nasty surprise to someone holding foop->lock2. So we >> now require CPUs to support single-byte and double-byte loads and stores. >> Therefore, this commit adjusts the definition of __native_word() to allow >> these sizes to be used by smp_load_acquire() and smp_store_release(). > > So does this patch depends on a patch that removes pre EV56 alpha > support? I'm all for removing that, but I need to see the patch merged > before we can do this. I'm working on that but Alpha's Kconfig is not quite straightforward. ... and I'm wondering if I should _remove_ pre-EV56 configurations or move the default choice and produce a warning about unsupported Alpha CPUs instead? Regards, Peter Hurley [ How does one do a red popup in kbuild? The 'comment' approach is too subtle. ] From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mailout32.mail01.mtsvc.net ([216.70.64.70]:37453 "EHLO n23.mail01.mtsvc.net" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1751346AbaIEUBs (ORCPT ); Fri, 5 Sep 2014 16:01:48 -0400 Message-ID: <540A169F.40906@hurleysoftware.com> Date: Fri, 05 Sep 2014 16:01:35 -0400 From: Peter Hurley MIME-Version: 1.0 Subject: Re: bit fields && data tearing References: <54079B70.4050200@hurleysoftware.com> <1409785893.30640.118.camel@pasglop> <063D6719AE5E284EB5DD2968C1650D6D17487172@AcuExch.aculab.com> <1409824374.4246.62.camel@pasglop> <5408E458.3@zytor.com> <54090AF4.7060406@hurleysoftware.com> <54091B30.2090509@zytor.com> <20140905081648.GB5281@omega> <20140905180950.GU5001@linux.vnet.ibm.com> <20140905183109.GA5497@linux.vnet.ibm.com> <20140905195234.GT4783@worktop.ger.corp.intel.com> In-Reply-To: <20140905195234.GT4783@worktop.ger.corp.intel.com> Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit Sender: linux-arch-owner@vger.kernel.org List-ID: To: Peter Zijlstra , "Paul E. McKenney" Cc: Michael Cree , "H. Peter Anvin" , Benjamin Herrenschmidt , David Laight , Jakub Jelinek , "linux-arch@vger.kernel.org" , Tony Luck , "linux-ia64@vger.kernel.org" , Oleg Nesterov , "linux-kernel@vger.kernel.org" , Paul Mackerras , "linuxppc-dev@lists.ozlabs.org" , Miroslav Franc , Richard Henderson , linux-alpha@vger.kernel.org Message-ID: <20140905200135.OOdpQWkE8Bn_ECw28gHPL-QrjIBnrNqlkcfV34j72rM@z> On 09/05/2014 03:52 PM, Peter Zijlstra wrote: > On Fri, Sep 05, 2014 at 11:31:09AM -0700, Paul E. McKenney wrote: >> compiler: Allow 1- and 2-byte smp_load_acquire() and smp_store_release() >> >> CPUs without single-byte and double-byte loads and stores place some >> "interesting" requirements on concurrent code. For example (adapted >> from Peter Hurley's test code), suppose we have the following structure: >> >> struct foo { >> spinlock_t lock1; >> spinlock_t lock2; >> char a; /* Protected by lock1. */ >> char b; /* Protected by lock2. */ >> }; >> struct foo *foop; >> >> Of course, it is common (and good) practice to place data protected >> by different locks in separate cache lines. However, if the locks are >> rarely acquired (for example, only in rare error cases), and there are >> a great many instances of the data structure, then memory footprint can >> trump false-sharing concerns, so that it can be better to place them in >> the same cache cache line as above. >> >> But if the CPU does not support single-byte loads and stores, a store >> to foop->a will do a non-atomic read-modify-write operation on foop->b, >> which will come as a nasty surprise to someone holding foop->lock2. So we >> now require CPUs to support single-byte and double-byte loads and stores. >> Therefore, this commit adjusts the definition of __native_word() to allow >> these sizes to be used by smp_load_acquire() and smp_store_release(). > > So does this patch depends on a patch that removes pre EV56 alpha > support? I'm all for removing that, but I need to see the patch merged > before we can do this. I'm working on that but Alpha's Kconfig is not quite straightforward. ... and I'm wondering if I should _remove_ pre-EV56 configurations or move the default choice and produce a warning about unsupported Alpha CPUs instead? Regards, Peter Hurley [ How does one do a red popup in kbuild? The 'comment' approach is too subtle. ]