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Wed, 13 Nov 2024 07:35:31 -0500 (EST) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: linux-arch@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Wed, 13 Nov 2024 13:35:10 +0100 From: "Arnd Bergmann" To: "Suravee Suthikulpanit" , linux-kernel@vger.kernel.org, iommu@lists.linux.dev Cc: "Joerg Roedel" , "Robin Murphy" , vasant.hegde@amd.com, "Uros Bizjak" , Linux-Arch , "Jason Gunthorpe" , "Kevin Tian" , jon.grimm@amd.com, santosh.shukla@amd.com, pandoh@google.com, kumaranand@google.com Message-Id: <558bf28e-6cf8-436d-b2ef-382ff421bb00@app.fastmail.com> In-Reply-To: <20241113120327.5239-3-suravee.suthikulpanit@amd.com> References: <20241113120327.5239-1-suravee.suthikulpanit@amd.com> <20241113120327.5239-3-suravee.suthikulpanit@amd.com> Subject: Re: [PATCH v10 02/10] iommu/amd: Disable AMD IOMMU if CMPXCHG16B feature is not supported Content-Type: text/plain Content-Transfer-Encoding: 7bit On Wed, Nov 13, 2024, at 13:03, Suravee Suthikulpanit wrote: > According to the AMD IOMMU spec, IOMMU hardware reads the entire DTE > in a single 256-bit transaction. It is recommended to update DTE using > 128-bit operation followed by an INVALIDATE_DEVTAB_ENTYRY command when > the IV=1b or V=1b before the change. > > According to the AMD BIOS and Kernel Developer's Guide (BDKG) dated back > to family 10h Processor [1], which is the first introduction of AMD IOMMU, > AMD processor always has CPUID Fn0000_0001_ECX[CMPXCHG16B]=1. > Therefore, it is safe to assume cmpxchg128 is available with all AMD > processor w/ IOMMU. Makes sense. More specifically, I'm fairly sure the only x86-64 CPUs without cmpxchg16b are very early NetBurst Xeons, while AMD had the instruction from the start, and dropping the runtime check entirely would work just as well. Arnd