From mboxrd@z Thu Jan 1 00:00:00 1970 From: Leonid Yegoshin Subject: Re: [v3,11/41] mips: reuse asm-generic/barrier.h Date: Thu, 14 Jan 2016 11:28:18 -0800 Message-ID: <5697F6D2.60409@imgtec.com> References: <1452426622-4471-12-git-send-email-mst@redhat.com> <56945366.2090504@imgtec.com> <20160112092711.GP6344@twins.programming.kicks-ass.net> <20160112102555.GV6373@twins.programming.kicks-ass.net> <20160112104012.GW6373@twins.programming.kicks-ass.net> <20160112114111.GB15737@arm.com> <569565DA.2010903@imgtec.com> <20160113104516.GE25458@arm.com> <5696CF08.8080700@imgtec.com> <20160114121449.GC15828@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20160114121449.GC15828@arm.com> Sender: linux-ia64-owner@vger.kernel.org To: Will Deacon Cc: Peter Zijlstra , "Michael S. Tsirkin" , linux-kernel@vger.kernel.org, Arnd Bergmann , linux-arch@vger.kernel.org, Andrew Cooper , Russell King - ARM Linux , virtualization@lists.linux-foundation.org, Stefano Stabellini , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Joe Perches , David Miller , linux-ia64@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-metag@vger.kernel.org, linux-mips@linux-mips.org, x86@kernel.org, user-mode-linux-devel@lists.sourceforge.net, adi-buildroot-devel@lists.sourceforge.net, linux-sh@vg List-Id: linux-arch.vger.kernel.org On 01/14/2016 04:14 AM, Will Deacon wrote: > On Wed, Jan 13, 2016 at 02:26:16PM -0800, Leonid Yegoshin wrote: > >> Moreover, there are voices against guarantee that it will be in future >> and that voices point me to Documentation/memory-barriers.txt section "DATA >> DEPENDENCY BARRIERS" examples which require SYNC_RMB between loading >> address/index and using that for loading data based on that address or index >> for shared data (look on CPU2 pseudo-code): >>> To deal with this, a data dependency barrier or better must be inserted >>> between the address load and the data load: >>> >>> CPU 1 CPU 2 >>> =============== =============== >>> { A == 1, B == 2, C = 3, P == &A, Q == &C } >>> B = 4; >>> >>> WRITE_ONCE(P, &B); >>> Q = READ_ONCE(P); >>> <----------- >>> SYNC_RMB is here >>> D = *Q; >> ... >>> Another example of where data dependency barriers might be required is >>> where a >>> number is read from memory and then used to calculate the index for an >>> array >>> access: >>> >>> CPU 1 CPU 2 >>> =============== =============== >>> { M[0] == 1, M[1] == 2, M[3] = 3, P == 0, Q == 3 } >>> M[1] = 4; >>> >>> WRITE_ONCE(P, 1); >>> Q = READ_ONCE(P); >>> <------------ >>> SYNC_RMB is here >>> D = M[Q]; >> That voices say that there is a legitimate reason to relax HW here for >> performance if SYNC_RMB is needed anyway to work with this sequence of >> shared data. > Are you saying that MIPS needs to implement [smp_]read_barrier_depends? It is not me, it is Documentation/memory-barriers.txt from kernel sources. HW team can't work on voice statements, it should do a work on written documents. If that is written (see above the lines which I marked by "SYNC_RMB") then anybody should use it and never mind how many CPUs/Threads are in play. This examples explicitly requires to insert "data dependency barrier" between reading a shared pointer/index and using it to fetch a shared data. So, your WRC+addr+addr test is a violation of that recommendation. - Leonid. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from [195.59.15.196] ([195.59.15.196]:58588 "EHLO mailapp01.imgtec.com" rhost-flags-FAIL-FAIL-OK-OK) by vger.kernel.org with ESMTP id S1756044AbcANT2u (ORCPT ); Thu, 14 Jan 2016 14:28:50 -0500 Message-ID: <5697F6D2.60409@imgtec.com> Date: Thu, 14 Jan 2016 11:28:18 -0800 From: Leonid Yegoshin MIME-Version: 1.0 Subject: Re: [v3,11/41] mips: reuse asm-generic/barrier.h References: <1452426622-4471-12-git-send-email-mst@redhat.com> <56945366.2090504@imgtec.com> <20160112092711.GP6344@twins.programming.kicks-ass.net> <20160112102555.GV6373@twins.programming.kicks-ass.net> <20160112104012.GW6373@twins.programming.kicks-ass.net> <20160112114111.GB15737@arm.com> <569565DA.2010903@imgtec.com> <20160113104516.GE25458@arm.com> <5696CF08.8080700@imgtec.com> <20160114121449.GC15828@arm.com> In-Reply-To: <20160114121449.GC15828@arm.com> Content-Type: text/plain; charset="windows-1252"; format=flowed Content-Transfer-Encoding: 7bit Sender: linux-arch-owner@vger.kernel.org List-ID: To: Will Deacon Cc: Peter Zijlstra , "Michael S. Tsirkin" , linux-kernel@vger.kernel.org, Arnd Bergmann , linux-arch@vger.kernel.org, Andrew Cooper , Russell King - ARM Linux , virtualization@lists.linux-foundation.org, Stefano Stabellini , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Joe Perches , David Miller , linux-ia64@vger.kernel.org, linuxppc-dev@lists.ozlabs.org, linux-s390@vger.kernel.org, sparclinux@vger.kernel.org, linux-arm-kernel@lists.infradead.org, linux-metag@vger.kernel.org, linux-mips@linux-mips.org, x86@kernel.org, user-mode-linux-devel@lists.sourceforge.net, adi-buildroot-devel@lists.sourceforge.net, linux-sh@vger.kernel.org, linux-xtensa@linux-xtensa.org, xen-devel@lists.xenproject.org, Ralf Baechle , Ingo Molnar , ddaney.cavm@gmail.com, james.hogan@imgtec.com, Michael Ellerman , Paul McKenney Message-ID: <20160114192818.2rPk80XHtMxf5vEf0Xhnam-L8JuhbzH2buU3SnfzO-I@z> On 01/14/2016 04:14 AM, Will Deacon wrote: > On Wed, Jan 13, 2016 at 02:26:16PM -0800, Leonid Yegoshin wrote: > >> Moreover, there are voices against guarantee that it will be in future >> and that voices point me to Documentation/memory-barriers.txt section "DATA >> DEPENDENCY BARRIERS" examples which require SYNC_RMB between loading >> address/index and using that for loading data based on that address or index >> for shared data (look on CPU2 pseudo-code): >>> To deal with this, a data dependency barrier or better must be inserted >>> between the address load and the data load: >>> >>> CPU 1 CPU 2 >>> =============== =============== >>> { A == 1, B == 2, C = 3, P == &A, Q == &C } >>> B = 4; >>> >>> WRITE_ONCE(P, &B); >>> Q = READ_ONCE(P); >>> <----------- >>> SYNC_RMB is here >>> D = *Q; >> ... >>> Another example of where data dependency barriers might be required is >>> where a >>> number is read from memory and then used to calculate the index for an >>> array >>> access: >>> >>> CPU 1 CPU 2 >>> =============== =============== >>> { M[0] == 1, M[1] == 2, M[3] = 3, P == 0, Q == 3 } >>> M[1] = 4; >>> >>> WRITE_ONCE(P, 1); >>> Q = READ_ONCE(P); >>> <------------ >>> SYNC_RMB is here >>> D = M[Q]; >> That voices say that there is a legitimate reason to relax HW here for >> performance if SYNC_RMB is needed anyway to work with this sequence of >> shared data. > Are you saying that MIPS needs to implement [smp_]read_barrier_depends? It is not me, it is Documentation/memory-barriers.txt from kernel sources. HW team can't work on voice statements, it should do a work on written documents. If that is written (see above the lines which I marked by "SYNC_RMB") then anybody should use it and never mind how many CPUs/Threads are in play. This examples explicitly requires to insert "data dependency barrier" between reading a shared pointer/index and using it to fetch a shared data. So, your WRC+addr+addr test is a violation of that recommendation. - Leonid.