From mboxrd@z Thu Jan 1 00:00:00 1970 From: David Howells Subject: Re: 1808d65b55 ("asm-generic/tlb: Remove arch_tlb*_mmu()"): BUG: KASAN: stack-out-of-bounds in __change_page_attr_set_clr Date: Fri, 12 Apr 2019 17:50:30 +0100 Message-ID: <5890.1555087830@warthog.procyon.org.uk> References: <5cae03c4.iIPk2cWlfmzP0Zgy%lkp@intel.com> <20190411193906.GA12232@hirez.programming.kicks-ass.net> <20190411195424.GL14281@hirez.programming.kicks-ass.net> <20190411211348.GA8451@worktop.programming.kicks-ass.net> <20190412105633.GM14281@hirez.programming.kicks-ass.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Return-path: In-Reply-To: Content-ID: <5889.1555087830.1@warthog.procyon.org.uk> Sender: linux-kernel-owner@vger.kernel.org To: Linus Torvalds Cc: dhowells@redhat.com, Peter Zijlstra , kernel test robot , LKP , Linux List Kernel Mailing , Linux-MM , linux-arch , Ingo Molnar , Thomas Gleixner , Will Deacon , Andy Lutomirski , Nadav Amit List-Id: linux-arch.vger.kernel.org Linus Torvalds wrote: > We should never have stack alignment bigger than 16 bytes. And > preferably not even that. At least one arch I know of (FRV) had instructions that could atomically load/store register pairs or register quads, but they had to be pair- or quad-aligned (ie. 8- or 16-byte), which made for more efficient code if you could use them. I don't know whether any arch we currently support has features like this (I know some have multi-reg load/stores, but they seem to require only word-alignment). David From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mx1.redhat.com ([209.132.183.28]:58688 "EHLO mx1.redhat.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1726624AbfDLQud (ORCPT ); Fri, 12 Apr 2019 12:50:33 -0400 From: David Howells In-Reply-To: References: <5cae03c4.iIPk2cWlfmzP0Zgy%lkp@intel.com> <20190411193906.GA12232@hirez.programming.kicks-ass.net> <20190411195424.GL14281@hirez.programming.kicks-ass.net> <20190411211348.GA8451@worktop.programming.kicks-ass.net> <20190412105633.GM14281@hirez.programming.kicks-ass.net> Subject: Re: 1808d65b55 ("asm-generic/tlb: Remove arch_tlb*_mmu()"): BUG: KASAN: stack-out-of-bounds in __change_page_attr_set_clr MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-ID: <5889.1555087830.1@warthog.procyon.org.uk> Date: Fri, 12 Apr 2019 17:50:30 +0100 Message-ID: <5890.1555087830@warthog.procyon.org.uk> Sender: linux-arch-owner@vger.kernel.org List-ID: To: Linus Torvalds Cc: dhowells@redhat.com, Peter Zijlstra , kernel test robot , LKP , Linux List Kernel Mailing , Linux-MM , linux-arch , Ingo Molnar , Thomas Gleixner , Will Deacon , Andy Lutomirski , Nadav Amit Message-ID: <20190412165030.3xjkXY0qqrFakn7firraT6sL0928UPcz4ge1i2WpOdQ@z> Linus Torvalds wrote: > We should never have stack alignment bigger than 16 bytes. And > preferably not even that. At least one arch I know of (FRV) had instructions that could atomically load/store register pairs or register quads, but they had to be pair- or quad-aligned (ie. 8- or 16-byte), which made for more efficient code if you could use them. I don't know whether any arch we currently support has features like this (I know some have multi-reg load/stores, but they seem to require only word-alignment). David