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Fri, 4 Oct 2024 09:21:28 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface Precedence: bulk X-Mailing-List: linux-arch@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Date: Fri, 04 Oct 2024 13:21:08 +0000 From: "Arnd Bergmann" To: "Vincenzo Frascino" , linux-kernel@vger.kernel.org, Linux-Arch , linux-mm@kvack.org Cc: "Andy Lutomirski" , "Thomas Gleixner" , "Jason A . Donenfeld" , "Christophe Leroy" , "Michael Ellerman" , "Nicholas Piggin" , "Naveen N Rao" , "Ingo Molnar" , "Borislav Petkov" , "Dave Hansen" , "H. Peter Anvin" , "Theodore Ts'o" , "Andrew Morton" , "Steven Rostedt" , "Masami Hiramatsu" , "Mathieu Desnoyers" Message-Id: <5b52dfcf-7b4c-4715-b1b2-6e41062302bd@app.fastmail.com> In-Reply-To: <20241003152910.3287259-2-vincenzo.frascino@arm.com> References: <20241003152910.3287259-1-vincenzo.frascino@arm.com> <20241003152910.3287259-2-vincenzo.frascino@arm.com> Subject: Re: [PATCH v3 1/2] drm: Fix fault format Content-Type: text/plain Content-Transfer-Encoding: 7bit On Thu, Oct 3, 2024, at 15:29, Vincenzo Frascino wrote: > diff --git a/drivers/gpu/drm/i915/gt/intel_gt.c > b/drivers/gpu/drm/i915/gt/intel_gt.c > index a6c69a706fd7..352ef5e1c615 100644 > --- a/drivers/gpu/drm/i915/gt/intel_gt.c > +++ b/drivers/gpu/drm/i915/gt/intel_gt.c > @@ -308,7 +308,7 @@ static void gen6_check_faults(struct intel_gt *gt) > fault = GEN6_RING_FAULT_REG_READ(engine); > if (fault & RING_FAULT_VALID) { > gt_dbg(gt, "Unexpected fault\n" > - "\tAddr: 0x%08lx\n" > + "\tAddr: 0x%08x\n" > "\tAddress space: %s\n" > "\tSource ID: %d\n" > "\tType: %d\n", Isn't the type of PAGE_MASK still architecture dependent? I think you need a cast to either 'int' or 'long' here to make the corresponding format string work across all architectures. With the current version of your patch 2/2, it looks like it has to be %x for architectures with 64-bit phys_addr_t, but %lx for the other ones. Changing the 'u32 fault' variable to 'unsigned long' would also work here. Arnd