From mboxrd@z Thu Jan 1 00:00:00 1970 From: Dave Hansen Subject: Re: [RFC PATCH v2 12/27] x86/mm: Shadow stack page fault error checking Date: Tue, 10 Jul 2018 15:52:55 -0700 Message-ID: <61793360-f37c-ec19-c390-abe3c76a5f5c@linux.intel.com> References: <20180710222639.8241-1-yu-cheng.yu@intel.com> <20180710222639.8241-13-yu-cheng.yu@intel.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 8bit Return-path: In-Reply-To: <20180710222639.8241-13-yu-cheng.yu@intel.com> Content-Language: en-US Sender: linux-kernel-owner@vger.kernel.org To: Yu-cheng Yu , x86@kernel.org, "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Andy Lutomirski , Balbir Singh , Cyrill Gorcunov , Florian Weimer , "H.J. Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra List-Id: linux-arch.vger.kernel.org On 07/10/2018 03:26 PM, Yu-cheng Yu wrote: > +++ b/arch/x86/include/asm/traps.h > @@ -157,6 +157,7 @@ enum { > * bit 3 == 1: use of reserved bit detected > * bit 4 == 1: fault was an instruction fetch > * bit 5 == 1: protection keys block access > + * bit 6 == 1: shadow stack access fault > */ Could we document this bit better? Is this a fault where the *processor* thought it should be a shadow stack fault? Or is it also set on faults to valid shadow stack PTEs that just happen to fault for other reasons, say protection keys? From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mga03.intel.com ([134.134.136.65]:22619 "EHLO mga03.intel.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1732340AbeGJWyN (ORCPT ); Tue, 10 Jul 2018 18:54:13 -0400 Subject: Re: [RFC PATCH v2 12/27] x86/mm: Shadow stack page fault error checking References: <20180710222639.8241-1-yu-cheng.yu@intel.com> <20180710222639.8241-13-yu-cheng.yu@intel.com> From: Dave Hansen Message-ID: <61793360-f37c-ec19-c390-abe3c76a5f5c@linux.intel.com> Date: Tue, 10 Jul 2018 15:52:55 -0700 MIME-Version: 1.0 In-Reply-To: <20180710222639.8241-13-yu-cheng.yu@intel.com> Content-Type: text/plain; charset=utf-8 Content-Language: en-US Content-Transfer-Encoding: 8bit Sender: linux-arch-owner@vger.kernel.org List-ID: To: Yu-cheng Yu , x86@kernel.org, "H. Peter Anvin" , Thomas Gleixner , Ingo Molnar , linux-kernel@vger.kernel.org, linux-doc@vger.kernel.org, linux-mm@kvack.org, linux-arch@vger.kernel.org, linux-api@vger.kernel.org, Arnd Bergmann , Andy Lutomirski , Balbir Singh , Cyrill Gorcunov , Florian Weimer , "H.J. Lu" , Jann Horn , Jonathan Corbet , Kees Cook , Mike Kravetz , Nadav Amit , Oleg Nesterov , Pavel Machek , Peter Zijlstra , "Ravi V. Shankar" , Vedvyas Shanbhogue Message-ID: <20180710225255.c9MgjCw1wadaNVUBIJ16-VdJq9XQjXRiHv7LkrD1q_g@z> On 07/10/2018 03:26 PM, Yu-cheng Yu wrote: > +++ b/arch/x86/include/asm/traps.h > @@ -157,6 +157,7 @@ enum { > * bit 3 == 1: use of reserved bit detected > * bit 4 == 1: fault was an instruction fetch > * bit 5 == 1: protection keys block access > + * bit 6 == 1: shadow stack access fault > */ Could we document this bit better? Is this a fault where the *processor* thought it should be a shadow stack fault? Or is it also set on faults to valid shadow stack PTEs that just happen to fault for other reasons, say protection keys?