From mboxrd@z Thu Jan 1 00:00:00 1970 From: Zhenyu Ye Subject: Re: [PATCH v1 1/6] arm64: Detect the ARMv8.4 TTL feature Date: Wed, 22 Apr 2020 10:13:39 +0800 Message-ID: <62414595-298a-da11-28eb-36ad1dc59e65@huawei.com> References: <20200403090048.938-1-yezhenyu2@huawei.com> <20200403090048.938-2-yezhenyu2@huawei.com> <20200421165346.GA11171@infradead.org> <20200421171328.GW20730@hirez.programming.kicks-ass.net> <20200421171641.GA25391@infradead.org> Mime-Version: 1.0 Content-Type: text/plain; charset="gbk" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20200421171641.GA25391@infradead.org> Sender: linux-kernel-owner@vger.kernel.org To: Christoph Hellwig , Peter Zijlstra Cc: mark.rutland@arm.com, will@kernel.org, catalin.marinas@arm.com, aneesh.kumar@linux.ibm.com, akpm@linux-foundation.org, npiggin@gmail.com, arnd@arndb.de, rostedt@goodmis.org, maz@kernel.org, suzuki.poulose@arm.com, tglx@linutronix.de, yuzhao@google.com, Dave.Martin@arm.com, steven.price@arm.com, broonie@kernel.org, guohanjun@huawei.com, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, xiexiangyou@huawei.com, zhangshaokun@hisilicon.com, linux-mm@kvack.org, arm@kernel.org, prime.zeng@hisilicon.com, kuhn.chenqun@huawei.com, linux-arm-kernel@lists.infradead.org List-Id: linux-arch.vger.kernel.org On 2020/4/22 1:16, Christoph Hellwig wrote: > On Tue, Apr 21, 2020 at 07:13:28PM +0200, Peter Zijlstra wrote: >> On Tue, Apr 21, 2020 at 09:53:46AM -0700, Christoph Hellwig wrote: >>> On Fri, Apr 03, 2020 at 05:00:43PM +0800, Zhenyu Ye wrote: >>>> From: Marc Zyngier >>>> >>>> In order to reduce the cost of TLB invalidation, the ARMv8.4 TTL >>>> feature allows TLBs to be issued with a level allowing for quicker >>>> invalidation. >>> >>> What does "issued with a level" mean? >> >> What I understood it to be is page-size based on page-table hierarchy. >> Just like we have on x86, 4k, 2m, 1g etc.. >> >> So where x86 INVLPG will tear down any sized page for the address given, >> you can now day, kill me the PMD level translation for @addr. >> >> Power9 radix also has things like this. > > Maybe this needs to be spelled out a little more? The current commit > log sounds like paper generated by a neural network. > Emm... This patch was synchronized from Marc's NV series [1]. "issued with a level" means the TLBs now can get which levels of page tables the @addr is in. You can also understand it as page-size as Peter said above, just like pud, pmd, pte... Anyway, I will explain this in more detail. Thanks, Zhenyu From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from szxga05-in.huawei.com ([45.249.212.191]:2827 "EHLO huawei.com" rhost-flags-OK-OK-OK-FAIL) by vger.kernel.org with ESMTP id S1726024AbgDVCNx (ORCPT ); Tue, 21 Apr 2020 22:13:53 -0400 Subject: Re: [PATCH v1 1/6] arm64: Detect the ARMv8.4 TTL feature References: <20200403090048.938-1-yezhenyu2@huawei.com> <20200403090048.938-2-yezhenyu2@huawei.com> <20200421165346.GA11171@infradead.org> <20200421171328.GW20730@hirez.programming.kicks-ass.net> <20200421171641.GA25391@infradead.org> From: Zhenyu Ye Message-ID: <62414595-298a-da11-28eb-36ad1dc59e65@huawei.com> Date: Wed, 22 Apr 2020 10:13:39 +0800 MIME-Version: 1.0 In-Reply-To: <20200421171641.GA25391@infradead.org> Content-Type: text/plain; charset="gbk" Content-Transfer-Encoding: 7bit Sender: linux-arch-owner@vger.kernel.org List-ID: To: Christoph Hellwig , Peter Zijlstra Cc: mark.rutland@arm.com, will@kernel.org, catalin.marinas@arm.com, aneesh.kumar@linux.ibm.com, akpm@linux-foundation.org, npiggin@gmail.com, arnd@arndb.de, rostedt@goodmis.org, maz@kernel.org, suzuki.poulose@arm.com, tglx@linutronix.de, yuzhao@google.com, Dave.Martin@arm.com, steven.price@arm.com, broonie@kernel.org, guohanjun@huawei.com, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, xiexiangyou@huawei.com, zhangshaokun@hisilicon.com, linux-mm@kvack.org, arm@kernel.org, prime.zeng@hisilicon.com, kuhn.chenqun@huawei.com, linux-arm-kernel@lists.infradead.org Message-ID: <20200422021339.ulN5-PpcPvfl5tyLvlZ8AbGbn-eXQmHQ8CKV4dDdDFI@z> On 2020/4/22 1:16, Christoph Hellwig wrote: > On Tue, Apr 21, 2020 at 07:13:28PM +0200, Peter Zijlstra wrote: >> On Tue, Apr 21, 2020 at 09:53:46AM -0700, Christoph Hellwig wrote: >>> On Fri, Apr 03, 2020 at 05:00:43PM +0800, Zhenyu Ye wrote: >>>> From: Marc Zyngier >>>> >>>> In order to reduce the cost of TLB invalidation, the ARMv8.4 TTL >>>> feature allows TLBs to be issued with a level allowing for quicker >>>> invalidation. >>> >>> What does "issued with a level" mean? >> >> What I understood it to be is page-size based on page-table hierarchy. >> Just like we have on x86, 4k, 2m, 1g etc.. >> >> So where x86 INVLPG will tear down any sized page for the address given, >> you can now day, kill me the PMD level translation for @addr. >> >> Power9 radix also has things like this. > > Maybe this needs to be spelled out a little more? The current commit > log sounds like paper generated by a neural network. > Emm... This patch was synchronized from Marc's NV series [1]. "issued with a level" means the TLBs now can get which levels of page tables the @addr is in. You can also understand it as page-size as Peter said above, just like pud, pmd, pte... Anyway, I will explain this in more detail. Thanks, Zhenyu