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Wed, 1 Jun 2022 08:10:00 -0400 (EDT) X-Mailer: MessagingEngine.com Webmail Interface User-Agent: Cyrus-JMAP/3.7.0-alpha0-591-gfe6c3a2700-fm-20220427.001-gfe6c3a27 Mime-Version: 1.0 Message-Id: <6e7da218-be6c-449d-92ea-be416ed12da5@www.fastmail.com> In-Reply-To: <20220601100005.2989022-3-chenhuacai@loongson.cn> References: <20220601100005.2989022-1-chenhuacai@loongson.cn> <20220601100005.2989022-3-chenhuacai@loongson.cn> Date: Wed, 01 Jun 2022 13:09:40 +0100 From: "Jiaxun Yang" To: "Huacai Chen" , "Arnd Bergmann" , "Andy Lutomirski" , "Thomas Gleixner" , "Peter Zijlstra" , "Andrew Morton" , "David Airlie" , "Jonathan Corbet" , "Linus Torvalds" Cc: linux-arch@vger.kernel.org, linux-doc@vger.kernel.org, linux-kernel@vger.kernel.org, "Xuefeng Li" , "Yanteng Si" , "Huacai Chen" , "Guo Ren" , "Xuerui Wang" , "Stephen Rothwell" Subject: Re: [PATCH V12 02/24] irqchip/loongson-liointc: Fix build error for LoongArch Content-Type: text/plain;charset=utf-8 Content-Transfer-Encoding: quoted-printable Precedence: bulk List-ID: X-Mailing-List: linux-arch@vger.kernel.org =E5=9C=A82022=E5=B9=B46=E6=9C=881=E6=97=A5=E5=85=AD=E6=9C=88 =E4=B8=8A=E5= =8D=8810:59=EF=BC=8CHuacai Chen=E5=86=99=E9=81=93=EF=BC=9A > liointc driver is shared by MIPS and LoongArch, this patch adjust the > code to fix build error for LoongArch. > > Signed-off-by: Huacai Chen Reviewed-by: Jiaxun Yang > --- > drivers/irqchip/irq-loongson-liointc.c | 6 +++++- > 1 file changed, 5 insertions(+), 1 deletion(-) > > diff --git a/drivers/irqchip/irq-loongson-liointc.c=20 > b/drivers/irqchip/irq-loongson-liointc.c > index 649c58391618..aed88857d90f 100644 > --- a/drivers/irqchip/irq-loongson-liointc.c > +++ b/drivers/irqchip/irq-loongson-liointc.c > @@ -16,7 +16,11 @@ > #include > #include >=20 > +#ifdef CONFIG_MIPS > #include > +#else > +#include > +#endif >=20 > #define LIOINTC_CHIP_IRQ 32 > #define LIOINTC_NUM_PARENT 4 > @@ -53,7 +57,7 @@ static void liointc_chained_handle_irq(struct irq_de= sc *desc) > struct liointc_handler_data *handler =3D irq_desc_get_handler_data(d= esc); > struct irq_chip *chip =3D irq_desc_get_chip(desc); > struct irq_chip_generic *gc =3D handler->priv->gc; > - int core =3D get_ebase_cpunum() % LIOINTC_NUM_CORES; > + int core =3D cpu_logical_map(smp_processor_id()) % LIOINTC_NUM_CORES; > u32 pending; >=20 > chained_irq_enter(chip, desc); > --=20 > 2.27.0 --=20 - Jiaxun