From mboxrd@z Thu Jan 1 00:00:00 1970 From: "stephane eranian" Subject: Re: [patch] Performance Counters for Linux, v2 Date: Wed, 10 Dec 2008 06:03:05 +0100 Message-ID: <7c86c4470812092103geca7df8ge9293de6de3f83ac@mail.gmail.com> References: <20081208012211.GA23106@elte.hu> <7c86c4470812082237ne58c814s7218cc663f3b49e9@mail.gmail.com> <20081209134636.GA1926@elte.hu> <18750.61143.101922.949701@cargo.ozlabs.ibm.com> <87skoxc6qo.fsf@basil.nowhere.org> <18751.18735.539555.111549@drongo.ozlabs.ibm.com> Reply-To: eranian@gmail.com Mime-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <18751.18735.539555.111549@drongo.ozlabs.ibm.com> Content-Disposition: inline Sender: linux-kernel-owner@vger.kernel.org To: Paul Mackerras Cc: Andi Kleen , Ingo Molnar , linux-kernel@vger.kernel.org, Thomas Gleixner , linux-arch@vger.kernel.org, Andrew Morton , Eric Dumazet , Robert Richter , Arjan van de Veen , Peter Anvin , Peter Zijlstra , Steven Rostedt , David Miller , Paolo Ciarrocchi List-Id: linux-arch.vger.kernel.org Paul, On Wed, Dec 10, 2008 at 5:44 AM, Paul Mackerras wrote: > Andi Kleen writes: > >> When you say counting you should also include "event ring buffers with >> metadata", like PEBS on Intel x86. > > I'm not familiar with PEBS. Maybe it's something different again, > neither sampling nor counting, but a third thing? > PEBS is an Intel only feature used for sampling. However, this time the hardware (and microcode) does the sampling for you. You point the CPU to a structure in memory, called DS, which then points to a region of memory you can designate, i.e., the sampling buffer. Buffer can be any size you want. Then you program counter0 when an event and a sampling period. When the counter overflows, there is no interrupt, the microcode records the RIP and full machine state, and reloads the counter with the period specified in DS. The OS gets an interrupt ONLY when the buffer fills up. Overhead is thus minimized, but you have no control over the format of the samples. The precision (P) comes from the fact that the RIP is guaranteed to point the an instruction that is just after an instruction which generated the event you're sampling on. The catch is that no all events support PEBS, and only one counter works with PEBS on Core 2. Nehalem is better, more events support PEBS, all 4 generic counters do support PEBS. Furthermore,PEBS can now capture where cache misses occur, very much like what Itanium can do. Needless to say all of this is supported by perfmon. Hope this helps. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-bw0-f13.google.com ([209.85.218.13]:54780 "EHLO mail-bw0-f13.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1749667AbYLJFDJ (ORCPT ); Wed, 10 Dec 2008 00:03:09 -0500 Received: by bwz6 with SMTP id 6so772778bwz.13 for ; Tue, 09 Dec 2008 21:03:06 -0800 (PST) Message-ID: <7c86c4470812092103geca7df8ge9293de6de3f83ac@mail.gmail.com> Date: Wed, 10 Dec 2008 06:03:05 +0100 From: "stephane eranian" Reply-To: eranian@gmail.com Subject: Re: [patch] Performance Counters for Linux, v2 In-Reply-To: <18751.18735.539555.111549@drongo.ozlabs.ibm.com> MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 7bit Content-Disposition: inline References: <20081208012211.GA23106@elte.hu> <7c86c4470812082237ne58c814s7218cc663f3b49e9@mail.gmail.com> <20081209134636.GA1926@elte.hu> <18750.61143.101922.949701@cargo.ozlabs.ibm.com> <87skoxc6qo.fsf@basil.nowhere.org> <18751.18735.539555.111549@drongo.ozlabs.ibm.com> Sender: linux-arch-owner@vger.kernel.org List-ID: To: Paul Mackerras Cc: Andi Kleen , Ingo Molnar , linux-kernel@vger.kernel.org, Thomas Gleixner , linux-arch@vger.kernel.org, Andrew Morton , Eric Dumazet , Robert Richter , Arjan van de Veen , Peter Anvin , Peter Zijlstra , Steven Rostedt , David Miller , Paolo Ciarrocchi Message-ID: <20081210050305.XXlJZX5vkH-NxGv00-wJkBubIGxKb4qQz5UIPvZYlDk@z> Paul, On Wed, Dec 10, 2008 at 5:44 AM, Paul Mackerras wrote: > Andi Kleen writes: > >> When you say counting you should also include "event ring buffers with >> metadata", like PEBS on Intel x86. > > I'm not familiar with PEBS. Maybe it's something different again, > neither sampling nor counting, but a third thing? > PEBS is an Intel only feature used for sampling. However, this time the hardware (and microcode) does the sampling for you. You point the CPU to a structure in memory, called DS, which then points to a region of memory you can designate, i.e., the sampling buffer. Buffer can be any size you want. Then you program counter0 when an event and a sampling period. When the counter overflows, there is no interrupt, the microcode records the RIP and full machine state, and reloads the counter with the period specified in DS. The OS gets an interrupt ONLY when the buffer fills up. Overhead is thus minimized, but you have no control over the format of the samples. The precision (P) comes from the fact that the RIP is guaranteed to point the an instruction that is just after an instruction which generated the event you're sampling on. The catch is that no all events support PEBS, and only one counter works with PEBS on Core 2. Nehalem is better, more events support PEBS, all 4 generic counters do support PEBS. Furthermore,PEBS can now capture where cache misses occur, very much like what Itanium can do. Needless to say all of this is supported by perfmon. Hope this helps.