From mboxrd@z Thu Jan 1 00:00:00 1970 From: Marc Zyngier Subject: Re: [PATCHv3 11/11] arm64: docs: document pointer authentication Date: Sun, 22 Apr 2018 09:47:29 +0100 Message-ID: <86h8o3r5jy.wl-marc.zyngier@arm.com> References: <20180417183735.56985-1-mark.rutland@arm.com> <20180417183735.56985-12-mark.rutland@arm.com> <20180422080520.GC17875@amd> Mime-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Return-path: In-Reply-To: <20180422080520.GC17875@amd> Sender: linux-kernel-owner@vger.kernel.org To: Pavel Machek Cc: Mark Rutland , linux-arm-kernel@lists.infradead.org, arnd@arndb.de, catalin.marinas@arm.com, cdall@kernel.org, drjones@redhat.com, kvmarm@lists.cs.columbia.edu, linux-arch@vger.kernel.org, ramana.radhakrishnan@arm.com, suzuki.poulose@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, awallis@codeaurora.org, kernel-hardening@lists.openwall.com List-Id: linux-arch.vger.kernel.org On Sun, 22 Apr 2018 09:05:21 +0100, Pavel Machek wrote: > > Hi! > > > @@ -205,6 +205,14 @@ Before jumping into the kernel, the following conditions must be met: > > ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0. > > - The DT or ACPI tables must describe a GICv2 interrupt controller. > > > > + For CPUs with pointer authentication functionality: > > + - If EL3 is present: > > + SCR_EL3.APK (bit 16) must be initialised to 0b1 > > + SCR_EL3.API (bit 17) must be initialised to 0b1 > > + - If the kernel is entered at EL1: > > + HCR_EL2.APK (bit 40) must be initialised to 0b1 > > + HCR_EL2.API (bit 41) must be initialised to 0b1 > > + > > 0b1 is quite confusing way to write 1. Do you find 0x1 equally confusing? 0bx is a pretty common way of describing bit-fields of a hardware register. It is also consistent with the rest of this document. M. -- Jazz is not dead, it just smell funny. From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from usa-sjc-mx-foss1.foss.arm.com ([217.140.101.70]:59262 "EHLO foss.arm.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1750854AbeDVIrh (ORCPT ); Sun, 22 Apr 2018 04:47:37 -0400 Date: Sun, 22 Apr 2018 09:47:29 +0100 Message-ID: <86h8o3r5jy.wl-marc.zyngier@arm.com> From: Marc Zyngier Subject: Re: [PATCHv3 11/11] arm64: docs: document pointer authentication In-Reply-To: <20180422080520.GC17875@amd> References: <20180417183735.56985-1-mark.rutland@arm.com> <20180417183735.56985-12-mark.rutland@arm.com> <20180422080520.GC17875@amd> MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII Sender: linux-arch-owner@vger.kernel.org List-ID: To: Pavel Machek Cc: Mark Rutland , linux-arm-kernel@lists.infradead.org, arnd@arndb.de, catalin.marinas@arm.com, cdall@kernel.org, drjones@redhat.com, kvmarm@lists.cs.columbia.edu, linux-arch@vger.kernel.org, ramana.radhakrishnan@arm.com, suzuki.poulose@arm.com, will.deacon@arm.com, linux-kernel@vger.kernel.org, awallis@codeaurora.org, kernel-hardening@lists.openwall.com Message-ID: <20180422084729.UJVjjPqjrcz2mUrzl-dfqRHizCdCmF0t5l2QHmHCvDI@z> On Sun, 22 Apr 2018 09:05:21 +0100, Pavel Machek wrote: > > Hi! > > > @@ -205,6 +205,14 @@ Before jumping into the kernel, the following conditions must be met: > > ICC_SRE_EL2.SRE (bit 0) must be initialised to 0b0. > > - The DT or ACPI tables must describe a GICv2 interrupt controller. > > > > + For CPUs with pointer authentication functionality: > > + - If EL3 is present: > > + SCR_EL3.APK (bit 16) must be initialised to 0b1 > > + SCR_EL3.API (bit 17) must be initialised to 0b1 > > + - If the kernel is entered at EL1: > > + HCR_EL2.APK (bit 40) must be initialised to 0b1 > > + HCR_EL2.API (bit 41) must be initialised to 0b1 > > + > > 0b1 is quite confusing way to write 1. Do you find 0x1 equally confusing? 0bx is a pretty common way of describing bit-fields of a hardware register. It is also consistent with the rest of this document. M. -- Jazz is not dead, it just smell funny.