From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: X-Spam-Checker-Version: SpamAssassin 3.4.0 (2014-02-07) on aws-us-west-2-korg-lkml-1.web.codeaurora.org Received: from vger.kernel.org (vger.kernel.org [23.128.96.18]) by smtp.lore.kernel.org (Postfix) with ESMTP id C35D3C25B06 for ; Tue, 9 Aug 2022 10:20:53 +0000 (UTC) Received: (majordomo@vger.kernel.org) by vger.kernel.org via listexpand id S231308AbiHIKUw (ORCPT ); Tue, 9 Aug 2022 06:20:52 -0400 Received: from lindbergh.monkeyblade.net ([23.128.96.19]:38974 "EHLO lindbergh.monkeyblade.net" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S242417AbiHIKUk (ORCPT ); Tue, 9 Aug 2022 06:20:40 -0400 Received: from dfw.source.kernel.org (dfw.source.kernel.org [IPv6:2604:1380:4641:c500::1]) by lindbergh.monkeyblade.net (Postfix) with ESMTPS id E7B9BAE4D; Tue, 9 Aug 2022 03:20:36 -0700 (PDT) Received: from smtp.kernel.org (relay.kernel.org [52.25.139.140]) (using TLSv1.2 with cipher ECDHE-RSA-AES256-GCM-SHA384 (256/256 bits)) (No client certificate requested) by dfw.source.kernel.org (Postfix) with ESMTPS id 5D99760F74; Tue, 9 Aug 2022 10:20:36 +0000 (UTC) Received: by smtp.kernel.org (Postfix) with ESMTPSA id BF5FCC433C1; Tue, 9 Aug 2022 10:20:35 +0000 (UTC) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/simple; d=kernel.org; s=k20201202; t=1660040435; bh=dOp1KDIuLoETirE7wJiLMR825TPGmbo2cZbIKOlhKRE=; h=Date:From:To:Cc:Subject:In-Reply-To:References:From; b=CsIkPOKC4kjYTl/GWLm7qdIZ6FQ7v8nt24VpTDpU0mwFTL15tGCGI1TO6gybUSnQ3 aD275hRPI7u1Gek1wUiCEm1ouqL5Dh+L0RKoWGsbnDuFVFSAry3mowHagmdDwvQTqc vRX3E9z81CrRUMWdDc3Ejsb9IWeN714yMlohvwbi8j+Y/Y3muwxQ3rW6F9dY9ly4s7 Aouu+WIKJRlt72JkQnmHTFCEv5IIoFGlMcZfXVGZYiPF3UMHmA8xtwUKOks2MP1inH zGND5heSYoDhryIkmEa5xxjP4abw4gvb1oD5XlwUGYluILcz89/nDUs98DQEGC7PDs BIuFtDsCN+qgw== Received: from sofa.misterjones.org ([185.219.108.64] helo=why.misterjones.org) by disco-boy.misterjones.org with esmtpsa (TLS1.3) tls TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384 (Exim 4.95) (envelope-from ) id 1oLMLh-001tEN-FK; Tue, 09 Aug 2022 11:20:33 +0100 Date: Tue, 09 Aug 2022 11:20:33 +0100 Message-ID: <871qtpwwem.wl-maz@kernel.org> From: Marc Zyngier To: Huacai Chen Cc: Huacai Chen , Thomas Gleixner , linux-arch , LKML , Xuerui Wang , Xuefeng Li , Jiaxun Yang Subject: Re: [PATCH] LoongArch: Don't disable EIOINTC master core In-Reply-To: References: <20220809074522.2444672-1-chenhuacai@loongson.cn> <874jylx0ad.wl-maz@kernel.org> User-Agent: Wanderlust/2.15.9 (Almost Unreal) SEMI-EPG/1.14.7 (Harue) FLIM-LB/1.14.9 (=?UTF-8?B?R29qxY0=?=) APEL-LB/10.8 EasyPG/1.0.0 Emacs/27.1 (x86_64-pc-linux-gnu) MULE/6.0 (HANACHIRUSATO) MIME-Version: 1.0 (generated by SEMI-EPG 1.14.7 - "Harue") Content-Type: text/plain; charset=US-ASCII X-SA-Exim-Connect-IP: 185.219.108.64 X-SA-Exim-Rcpt-To: chenhuacai@kernel.org, chenhuacai@loongson.cn, tglx@linutronix.de, linux-arch@vger.kernel.org, linux-kernel@vger.kernel.org, kernel@xen0n.name, lixuefeng@loongson.cn, jiaxun.yang@flygoat.com X-SA-Exim-Mail-From: maz@kernel.org X-SA-Exim-Scanned: No (on disco-boy.misterjones.org); SAEximRunCond expanded to false Precedence: bulk List-ID: X-Mailing-List: linux-arch@vger.kernel.org On Tue, 09 Aug 2022 10:19:31 +0100, Huacai Chen wrote: > > Hi, Marc, > > On Tue, Aug 9, 2022 at 4:56 PM Marc Zyngier wrote: > > > > On Tue, 09 Aug 2022 08:45:22 +0100, > > Huacai Chen wrote: > > > > > > This patch fix a CPU hotplug issue. The EIOINTC master core (the first > > > core of an EIOINTC node) should not be disabled at runtime, since it has > > > the responsibility of dispatching I/O interrupts. > > > > > > Signed-off-by: Huacai Chen > > > --- > > > arch/loongarch/kernel/smp.c | 9 +++++++++ > > > drivers/irqchip/irq-loongson-eiointc.c | 5 +++++ > > > 2 files changed, 14 insertions(+) > > > > > > diff --git a/arch/loongarch/kernel/smp.c b/arch/loongarch/kernel/smp.c > > > index 09743103d9b3..54901716f8de 100644 > > > --- a/arch/loongarch/kernel/smp.c > > > +++ b/arch/loongarch/kernel/smp.c > > > @@ -242,9 +242,18 @@ void loongson3_smp_finish(void) > > > > > > static bool io_master(int cpu) > > > { > > > + int i, node, master; > > > + > > > if (cpu == 0) > > > return true; > > > > > > + for (i = 1; i < loongson_sysconf.nr_io_pics; i++) { > > > + node = eiointc_get_node(i); > > > + master = cpu_number_map(node * CORES_PER_EIO_NODE); > > > + if (cpu == master) > > > + return true; > > > + } > > > + > > > return false; > > > } > > > > > > diff --git a/drivers/irqchip/irq-loongson-eiointc.c b/drivers/irqchip/irq-loongson-eiointc.c > > > index 170dbc96c7d3..6c99a2ff95f5 100644 > > > --- a/drivers/irqchip/irq-loongson-eiointc.c > > > +++ b/drivers/irqchip/irq-loongson-eiointc.c > > > @@ -56,6 +56,11 @@ static void eiointc_enable(void) > > > iocsr_write64(misc, LOONGARCH_IOCSR_MISC_FUNC); > > > } > > > > > > +int eiointc_get_node(int id) > > > +{ > > > + return eiointc_priv[id]->node; > > > +} > > > + > > > static int cpu_to_eio_node(int cpu) > > > { > > > return cpu_logical_map(cpu) / CORES_PER_EIO_NODE; > > > > > > I don't understand why it has to be this complex and make any use of > > the node number. > > > > As I understand it, CPU-0 in any EIOINTC block is a master. So all you > > need to find out is whether the CPU number is a multiple of > > CORES_PER_EIO_NODE. > CPU-0 in any EIOINTC block may be a master, but not absolutely be a > master to dispatch I/O interrupts. If there is no bridge under a > EIOINTC, then this EIOINTC doesn't handle I/O interrupts, and it can > be disabled at runtime. But that's not what your code is checking, is it? You're only reporting the node number, irrespective of whether there is anything behind the EIOINTC. M. -- Without deviation from the norm, progress is not possible.