From mboxrd@z Thu Jan 1 00:00:00 1970 From: Alex =?utf-8?Q?Benn=C3=A9e?= Subject: Re: [PATCH v5 12/30] arm64/sve: Low-level CPU setup Date: Wed, 08 Nov 2017 16:37:51 +0000 Message-ID: <87efp8rajk.fsf@linaro.org> References: <1509465082-30427-1-git-send-email-Dave.Martin@arm.com> <1509465082-30427-13-git-send-email-Dave.Martin@arm.com> Mime-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Return-path: Received: from mail-wr0-f194.google.com ([209.85.128.194]:54427 "EHLO mail-wr0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751763AbdKHQhx (ORCPT ); Wed, 8 Nov 2017 11:37:53 -0500 Received: by mail-wr0-f194.google.com with SMTP id l22so2971122wrc.11 for ; Wed, 08 Nov 2017 08:37:53 -0800 (PST) In-reply-to: <1509465082-30427-13-git-send-email-Dave.Martin@arm.com> Sender: linux-arch-owner@vger.kernel.org List-ID: To: Dave Martin Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Ard Biesheuvel , Szabolcs Nagy , Okamoto Takayuki , kvmarm@lists.cs.columbia.edu, libc-alpha@sourceware.org, linux-arch@vger.kernel.org Dave Martin writes: > To enable the kernel to use SVE, SVE traps from EL1 to EL2 must be > disabled. To take maximum advantage of the hardware, the full > available vector length also needs to be enabled for EL1 by > programming ZCR_EL2.LEN. (The kernel will program ZCR_EL1.LEN as > required, but this cannot override the limit set by ZCR_EL2.) > > This patch makes the appropriate changes to the EL2 early setup > code. > > Signed-off-by: Dave Martin > Reviewed-by: Catalin Marinas > Cc: Alex Benn=C3=A9e > > --- > > **Dropped at v3** Reviewed-by: Alex Benn=C3=A9e > (Due to significant changes to the logic.) Have it back: Reviewed-by: Alex Benn=C3=A9e > --- > arch/arm64/kernel/head.S | 13 ++++++++++++- > 1 file changed, 12 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S > index cfa90a4..67e86a0 100644 > --- a/arch/arm64/kernel/head.S > +++ b/arch/arm64/kernel/head.S > @@ -524,8 +524,19 @@ CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and = E0E on LE systems > mov x0, #0x33ff > msr cptr_el2, x0 // Disable copro. traps to EL2 > > + /* SVE register access */ > + mrs x1, id_aa64pfr0_el1 > + ubfx x1, x1, #ID_AA64PFR0_SVE_SHIFT, #4 > + cbz x1, 7f > + > + bic x0, x0, #CPTR_EL2_TZ // Also disable SVE traps > + msr cptr_el2, x0 // Disable copro. traps to EL2 > + isb > + mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector > + msr_s SYS_ZCR_EL2, x1 // length for EL1. > + > /* Hypervisor stub */ > - adr_l x0, __hyp_stub_vectors > +7: adr_l x0, __hyp_stub_vectors > msr vbar_el2, x0 > > /* spsr */ From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr0-f194.google.com ([209.85.128.194]:54427 "EHLO mail-wr0-f194.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1751763AbdKHQhx (ORCPT ); Wed, 8 Nov 2017 11:37:53 -0500 Received: by mail-wr0-f194.google.com with SMTP id l22so2971122wrc.11 for ; Wed, 08 Nov 2017 08:37:53 -0800 (PST) References: <1509465082-30427-1-git-send-email-Dave.Martin@arm.com> <1509465082-30427-13-git-send-email-Dave.Martin@arm.com> From: Alex =?utf-8?Q?Benn=C3=A9e?= Subject: Re: [PATCH v5 12/30] arm64/sve: Low-level CPU setup In-reply-to: <1509465082-30427-13-git-send-email-Dave.Martin@arm.com> Date: Wed, 08 Nov 2017 16:37:51 +0000 Message-ID: <87efp8rajk.fsf@linaro.org> MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: quoted-printable Sender: linux-arch-owner@vger.kernel.org List-ID: To: Dave Martin Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas , Will Deacon , Ard Biesheuvel , Szabolcs Nagy , Okamoto Takayuki , kvmarm@lists.cs.columbia.edu, libc-alpha@sourceware.org, linux-arch@vger.kernel.org Message-ID: <20171108163751.tbpqFZDBMkF3LtxSOSU5Cel7P_blG3KLFm8MVJD_NuE@z> Dave Martin writes: > To enable the kernel to use SVE, SVE traps from EL1 to EL2 must be > disabled. To take maximum advantage of the hardware, the full > available vector length also needs to be enabled for EL1 by > programming ZCR_EL2.LEN. (The kernel will program ZCR_EL1.LEN as > required, but this cannot override the limit set by ZCR_EL2.) > > This patch makes the appropriate changes to the EL2 early setup > code. > > Signed-off-by: Dave Martin > Reviewed-by: Catalin Marinas > Cc: Alex Benn=C3=A9e > > --- > > **Dropped at v3** Reviewed-by: Alex Benn=C3=A9e > (Due to significant changes to the logic.) Have it back: Reviewed-by: Alex Benn=C3=A9e > --- > arch/arm64/kernel/head.S | 13 ++++++++++++- > 1 file changed, 12 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/kernel/head.S b/arch/arm64/kernel/head.S > index cfa90a4..67e86a0 100644 > --- a/arch/arm64/kernel/head.S > +++ b/arch/arm64/kernel/head.S > @@ -524,8 +524,19 @@ CPU_LE( movk x0, #0x30d0, lsl #16 ) // Clear EE and = E0E on LE systems > mov x0, #0x33ff > msr cptr_el2, x0 // Disable copro. traps to EL2 > > + /* SVE register access */ > + mrs x1, id_aa64pfr0_el1 > + ubfx x1, x1, #ID_AA64PFR0_SVE_SHIFT, #4 > + cbz x1, 7f > + > + bic x0, x0, #CPTR_EL2_TZ // Also disable SVE traps > + msr cptr_el2, x0 // Disable copro. traps to EL2 > + isb > + mov x1, #ZCR_ELx_LEN_MASK // SVE: Enable full vector > + msr_s SYS_ZCR_EL2, x1 // length for EL1. > + > /* Hypervisor stub */ > - adr_l x0, __hyp_stub_vectors > +7: adr_l x0, __hyp_stub_vectors > msr vbar_el2, x0 > > /* spsr */ -- Alex Benn=C3=A9e