From: "Alex Bennée" <alex.bennee@linaro.org> To: Dave Martin <Dave.Martin@arm.com> Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will.deacon@arm.com>, Ard Biesheuvel <ard.biesheuvel@linaro.org>, Szabolcs Nagy <szabolcs.nagy@arm.com>, Okamoto Takayuki <tokamoto@jp.fujitsu.com>, kvmarm@lists.cs.columbia.edu, libc-alpha@sourceware.org, linux-arch@vger.kernel.org Subject: Re: [PATCH v5 11/30] arm64/sve: Signal frame and context structure definition Date: Wed, 08 Nov 2017 16:34:03 +0000 [thread overview] Message-ID: <87fu9orapw.fsf@linaro.org> (raw) In-Reply-To: <1509465082-30427-12-git-send-email-Dave.Martin@arm.com> Dave Martin <Dave.Martin@arm.com> writes: > This patch defines the representation that will be used for the SVE > register state in the signal frame, and implements support for > saving and restoring the SVE registers around signals. > > The same layout will also be used for the in-kernel task state. > > Due to the variability of the SVE vector length, it is not possible > to define a fixed C struct to describe all the registers. Instead, > Macros are defined in sigcontext.h to facilitate access to the > parts of the structure. > > Signed-off-by: Dave Martin <Dave.Martin@arm.com> > Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> > Cc: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > --- > arch/arm64/include/uapi/asm/sigcontext.h | 117 ++++++++++++++++++++++++++++++- > 1 file changed, 116 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/uapi/asm/sigcontext.h b/arch/arm64/include/uapi/asm/sigcontext.h > index f0a76b9..7654a81 100644 > --- a/arch/arm64/include/uapi/asm/sigcontext.h > +++ b/arch/arm64/include/uapi/asm/sigcontext.h > @@ -16,6 +16,8 @@ > #ifndef _UAPI__ASM_SIGCONTEXT_H > #define _UAPI__ASM_SIGCONTEXT_H > > +#ifndef __ASSEMBLY__ > + > #include <linux/types.h> > > /* > @@ -41,10 +43,11 @@ struct sigcontext { > * > * 0x210 fpsimd_context > * 0x10 esr_context > + * 0x8a0 sve_context (vl <= 64) (optional) > * 0x20 extra_context (optional) > * 0x10 terminator (null _aarch64_ctx) > * > - * 0xdb0 (reserved for future allocation) > + * 0x510 (reserved for future allocation) > * > * New records that can exceed this space need to be opt-in for userspace, so > * that an expanded signal frame is not generated unexpectedly. The mechanism > @@ -116,4 +119,116 @@ struct extra_context { > __u32 __reserved[3]; > }; > > +#define SVE_MAGIC 0x53564501 > + > +struct sve_context { > + struct _aarch64_ctx head; > + __u16 vl; > + __u16 __reserved[3]; > +}; > + > +#endif /* !__ASSEMBLY__ */ > + > +/* > + * The SVE architecture leaves space for future expansion of the > + * vector length beyond its initial architectural limit of 2048 bits > + * (16 quadwords). > + */ > +#define SVE_VQ_BYTES 16 /* number of bytes per quadword */ > + > +#define SVE_VQ_MIN 1 > +#define SVE_VQ_MAX 512 > + > +#define SVE_VL_MIN (SVE_VQ_MIN * SVE_VQ_BYTES) > +#define SVE_VL_MAX (SVE_VQ_MAX * SVE_VQ_BYTES) > + > +#define SVE_NUM_ZREGS 32 > +#define SVE_NUM_PREGS 16 > + > +#define sve_vl_valid(vl) \ > + ((vl) % SVE_VQ_BYTES == 0 && (vl) >= SVE_VL_MIN && (vl) <= SVE_VL_MAX) > +#define sve_vq_from_vl(vl) ((vl) / SVE_VQ_BYTES) > +#define sve_vl_from_vq(vq) ((vq) * SVE_VQ_BYTES) > + > +/* > + * If the SVE registers are currently live for the thread at signal delivery, > + * sve_context.head.size >= > + * SVE_SIG_CONTEXT_SIZE(sve_vq_from_vl(sve_context.vl)) > + * and the register data may be accessed using the SVE_SIG_*() macros. > + * > + * If sve_context.head.size < > + * SVE_SIG_CONTEXT_SIZE(sve_vq_from_vl(sve_context.vl)), > + * the SVE registers were not live for the thread and no register data > + * is included: in this case, the SVE_SIG_*() macros should not be > + * used except for this check. > + * > + * The same convention applies when returning from a signal: a caller > + * will need to remove or resize the sve_context block if it wants to > + * make the SVE registers live when they were previously non-live or > + * vice-versa. This may require the the caller to allocate fresh > + * memory and/or move other context blocks in the signal frame. > + * > + * Changing the vector length during signal return is not permitted: > + * sve_context.vl must equal the thread's current vector length when > + * doing a sigreturn. > + * > + * > + * Note: for all these macros, the "vq" argument denotes the SVE > + * vector length in quadwords (i.e., units of 128 bits). > + * > + * The correct way to obtain vq is to use sve_vq_from_vl(vl). The > + * result is valid if and only if sve_vl_valid(vl) is true. This is > + * guaranteed for a struct sve_context written by the kernel. > + * > + * > + * Additional macros describe the contents and layout of the payload. > + * For each, SVE_SIG_x_OFFSET(args) is the start offset relative to > + * the start of struct sve_context, and SVE_SIG_x_SIZE(args) is the > + * size in bytes: > + * > + * x type description > + * - ---- ----------- > + * REGS the entire SVE context > + * > + * ZREGS __uint128_t[SVE_NUM_ZREGS][vq] all Z-registers > + * ZREG __uint128_t[vq] individual Z-register Zn > + * > + * PREGS uint16_t[SVE_NUM_PREGS][vq] all P-registers > + * PREG uint16_t[vq] individual P-register Pn > + * > + * FFR uint16_t[vq] first-fault status register > + * > + * Additional data might be appended in the future. > + */ > + > +#define SVE_SIG_ZREG_SIZE(vq) ((__u32)(vq) * SVE_VQ_BYTES) > +#define SVE_SIG_PREG_SIZE(vq) ((__u32)(vq) * (SVE_VQ_BYTES / 8)) > +#define SVE_SIG_FFR_SIZE(vq) SVE_SIG_PREG_SIZE(vq) > + > +#define SVE_SIG_REGS_OFFSET \ > + ((sizeof(struct sve_context) + (SVE_VQ_BYTES - 1)) \ > + / SVE_VQ_BYTES * SVE_VQ_BYTES) > + > +#define SVE_SIG_ZREGS_OFFSET SVE_SIG_REGS_OFFSET > +#define SVE_SIG_ZREG_OFFSET(vq, n) \ > + (SVE_SIG_ZREGS_OFFSET + SVE_SIG_ZREG_SIZE(vq) * (n)) > +#define SVE_SIG_ZREGS_SIZE(vq) \ > + (SVE_SIG_ZREG_OFFSET(vq, SVE_NUM_ZREGS) - SVE_SIG_ZREGS_OFFSET) > + > +#define SVE_SIG_PREGS_OFFSET(vq) \ > + (SVE_SIG_ZREGS_OFFSET + SVE_SIG_ZREGS_SIZE(vq)) > +#define SVE_SIG_PREG_OFFSET(vq, n) \ > + (SVE_SIG_PREGS_OFFSET(vq) + SVE_SIG_PREG_SIZE(vq) * (n)) > +#define SVE_SIG_PREGS_SIZE(vq) \ > + (SVE_SIG_PREG_OFFSET(vq, SVE_NUM_PREGS) - SVE_SIG_PREGS_OFFSET(vq)) > + > +#define SVE_SIG_FFR_OFFSET(vq) \ > + (SVE_SIG_PREGS_OFFSET(vq) + SVE_SIG_PREGS_SIZE(vq)) > + > +#define SVE_SIG_REGS_SIZE(vq) \ > + (SVE_SIG_FFR_OFFSET(vq) + SVE_SIG_FFR_SIZE(vq) - SVE_SIG_REGS_OFFSET) > + > +#define SVE_SIG_CONTEXT_SIZE(vq) (SVE_SIG_REGS_OFFSET + SVE_SIG_REGS_SIZE(vq)) > + > + > #endif /* _UAPI__ASM_SIGCONTEXT_H */
WARNING: multiple messages have this Message-ID (diff)
From: "Alex Bennée" <alex.bennee@linaro.org> To: Dave Martin <Dave.Martin@arm.com> Cc: linux-arm-kernel@lists.infradead.org, Catalin Marinas <catalin.marinas@arm.com>, Will Deacon <will.deacon@arm.com>, Ard Biesheuvel <ard.biesheuvel@linaro.org>, Szabolcs Nagy <szabolcs.nagy@arm.com>, Okamoto Takayuki <tokamoto@jp.fujitsu.com>, kvmarm@lists.cs.columbia.edu, libc-alpha@sourceware.org, linux-arch@vger.kernel.org Subject: Re: [PATCH v5 11/30] arm64/sve: Signal frame and context structure definition Date: Wed, 08 Nov 2017 16:34:03 +0000 [thread overview] Message-ID: <87fu9orapw.fsf@linaro.org> (raw) Message-ID: <20171108163403.AF6R8Y78EEdshlWYgWhq7LrmEwj_-ACWXHNIzyxdCt0@z> (raw) In-Reply-To: <1509465082-30427-12-git-send-email-Dave.Martin@arm.com> Dave Martin <Dave.Martin@arm.com> writes: > This patch defines the representation that will be used for the SVE > register state in the signal frame, and implements support for > saving and restoring the SVE registers around signals. > > The same layout will also be used for the in-kernel task state. > > Due to the variability of the SVE vector length, it is not possible > to define a fixed C struct to describe all the registers. Instead, > Macros are defined in sigcontext.h to facilitate access to the > parts of the structure. > > Signed-off-by: Dave Martin <Dave.Martin@arm.com> > Reviewed-by: Catalin Marinas <catalin.marinas@arm.com> > Cc: Alex Bennée <alex.bennee@linaro.org> Reviewed-by: Alex Bennée <alex.bennee@linaro.org> > --- > arch/arm64/include/uapi/asm/sigcontext.h | 117 ++++++++++++++++++++++++++++++- > 1 file changed, 116 insertions(+), 1 deletion(-) > > diff --git a/arch/arm64/include/uapi/asm/sigcontext.h b/arch/arm64/include/uapi/asm/sigcontext.h > index f0a76b9..7654a81 100644 > --- a/arch/arm64/include/uapi/asm/sigcontext.h > +++ b/arch/arm64/include/uapi/asm/sigcontext.h > @@ -16,6 +16,8 @@ > #ifndef _UAPI__ASM_SIGCONTEXT_H > #define _UAPI__ASM_SIGCONTEXT_H > > +#ifndef __ASSEMBLY__ > + > #include <linux/types.h> > > /* > @@ -41,10 +43,11 @@ struct sigcontext { > * > * 0x210 fpsimd_context > * 0x10 esr_context > + * 0x8a0 sve_context (vl <= 64) (optional) > * 0x20 extra_context (optional) > * 0x10 terminator (null _aarch64_ctx) > * > - * 0xdb0 (reserved for future allocation) > + * 0x510 (reserved for future allocation) > * > * New records that can exceed this space need to be opt-in for userspace, so > * that an expanded signal frame is not generated unexpectedly. The mechanism > @@ -116,4 +119,116 @@ struct extra_context { > __u32 __reserved[3]; > }; > > +#define SVE_MAGIC 0x53564501 > + > +struct sve_context { > + struct _aarch64_ctx head; > + __u16 vl; > + __u16 __reserved[3]; > +}; > + > +#endif /* !__ASSEMBLY__ */ > + > +/* > + * The SVE architecture leaves space for future expansion of the > + * vector length beyond its initial architectural limit of 2048 bits > + * (16 quadwords). > + */ > +#define SVE_VQ_BYTES 16 /* number of bytes per quadword */ > + > +#define SVE_VQ_MIN 1 > +#define SVE_VQ_MAX 512 > + > +#define SVE_VL_MIN (SVE_VQ_MIN * SVE_VQ_BYTES) > +#define SVE_VL_MAX (SVE_VQ_MAX * SVE_VQ_BYTES) > + > +#define SVE_NUM_ZREGS 32 > +#define SVE_NUM_PREGS 16 > + > +#define sve_vl_valid(vl) \ > + ((vl) % SVE_VQ_BYTES == 0 && (vl) >= SVE_VL_MIN && (vl) <= SVE_VL_MAX) > +#define sve_vq_from_vl(vl) ((vl) / SVE_VQ_BYTES) > +#define sve_vl_from_vq(vq) ((vq) * SVE_VQ_BYTES) > + > +/* > + * If the SVE registers are currently live for the thread at signal delivery, > + * sve_context.head.size >= > + * SVE_SIG_CONTEXT_SIZE(sve_vq_from_vl(sve_context.vl)) > + * and the register data may be accessed using the SVE_SIG_*() macros. > + * > + * If sve_context.head.size < > + * SVE_SIG_CONTEXT_SIZE(sve_vq_from_vl(sve_context.vl)), > + * the SVE registers were not live for the thread and no register data > + * is included: in this case, the SVE_SIG_*() macros should not be > + * used except for this check. > + * > + * The same convention applies when returning from a signal: a caller > + * will need to remove or resize the sve_context block if it wants to > + * make the SVE registers live when they were previously non-live or > + * vice-versa. This may require the the caller to allocate fresh > + * memory and/or move other context blocks in the signal frame. > + * > + * Changing the vector length during signal return is not permitted: > + * sve_context.vl must equal the thread's current vector length when > + * doing a sigreturn. > + * > + * > + * Note: for all these macros, the "vq" argument denotes the SVE > + * vector length in quadwords (i.e., units of 128 bits). > + * > + * The correct way to obtain vq is to use sve_vq_from_vl(vl). The > + * result is valid if and only if sve_vl_valid(vl) is true. This is > + * guaranteed for a struct sve_context written by the kernel. > + * > + * > + * Additional macros describe the contents and layout of the payload. > + * For each, SVE_SIG_x_OFFSET(args) is the start offset relative to > + * the start of struct sve_context, and SVE_SIG_x_SIZE(args) is the > + * size in bytes: > + * > + * x type description > + * - ---- ----------- > + * REGS the entire SVE context > + * > + * ZREGS __uint128_t[SVE_NUM_ZREGS][vq] all Z-registers > + * ZREG __uint128_t[vq] individual Z-register Zn > + * > + * PREGS uint16_t[SVE_NUM_PREGS][vq] all P-registers > + * PREG uint16_t[vq] individual P-register Pn > + * > + * FFR uint16_t[vq] first-fault status register > + * > + * Additional data might be appended in the future. > + */ > + > +#define SVE_SIG_ZREG_SIZE(vq) ((__u32)(vq) * SVE_VQ_BYTES) > +#define SVE_SIG_PREG_SIZE(vq) ((__u32)(vq) * (SVE_VQ_BYTES / 8)) > +#define SVE_SIG_FFR_SIZE(vq) SVE_SIG_PREG_SIZE(vq) > + > +#define SVE_SIG_REGS_OFFSET \ > + ((sizeof(struct sve_context) + (SVE_VQ_BYTES - 1)) \ > + / SVE_VQ_BYTES * SVE_VQ_BYTES) > + > +#define SVE_SIG_ZREGS_OFFSET SVE_SIG_REGS_OFFSET > +#define SVE_SIG_ZREG_OFFSET(vq, n) \ > + (SVE_SIG_ZREGS_OFFSET + SVE_SIG_ZREG_SIZE(vq) * (n)) > +#define SVE_SIG_ZREGS_SIZE(vq) \ > + (SVE_SIG_ZREG_OFFSET(vq, SVE_NUM_ZREGS) - SVE_SIG_ZREGS_OFFSET) > + > +#define SVE_SIG_PREGS_OFFSET(vq) \ > + (SVE_SIG_ZREGS_OFFSET + SVE_SIG_ZREGS_SIZE(vq)) > +#define SVE_SIG_PREG_OFFSET(vq, n) \ > + (SVE_SIG_PREGS_OFFSET(vq) + SVE_SIG_PREG_SIZE(vq) * (n)) > +#define SVE_SIG_PREGS_SIZE(vq) \ > + (SVE_SIG_PREG_OFFSET(vq, SVE_NUM_PREGS) - SVE_SIG_PREGS_OFFSET(vq)) > + > +#define SVE_SIG_FFR_OFFSET(vq) \ > + (SVE_SIG_PREGS_OFFSET(vq) + SVE_SIG_PREGS_SIZE(vq)) > + > +#define SVE_SIG_REGS_SIZE(vq) \ > + (SVE_SIG_FFR_OFFSET(vq) + SVE_SIG_FFR_SIZE(vq) - SVE_SIG_REGS_OFFSET) > + > +#define SVE_SIG_CONTEXT_SIZE(vq) (SVE_SIG_REGS_OFFSET + SVE_SIG_REGS_SIZE(vq)) > + > + > #endif /* _UAPI__ASM_SIGCONTEXT_H */ -- Alex Bennée
next prev parent reply other threads:[~2017-11-08 16:34 UTC|newest] Thread overview: 106+ messages / expand[flat|nested] mbox.gz Atom feed top 2017-10-31 15:50 [PATCH v5 00/30] ARM Scalable Vector Extension (SVE) Dave Martin 2017-10-31 15:50 ` Dave Martin 2017-10-31 15:50 ` [PATCH v5 01/30] regset: Add support for dynamically sized regsets Dave Martin 2017-11-01 11:42 ` Catalin Marinas 2017-11-01 13:16 ` Dave Martin 2017-11-01 13:16 ` Dave Martin 2017-11-08 11:50 ` Alex Bennée 2017-11-08 11:50 ` Alex Bennée 2017-10-31 15:50 ` [PATCH v5 02/30] arm64: fpsimd: Correctly annotate exception helpers called from asm Dave Martin 2017-10-31 15:50 ` Dave Martin 2017-11-01 11:42 ` Catalin Marinas 2017-10-31 15:50 ` [PATCH v5 03/30] arm64: signal: Verify extra data is user-readable in sys_rt_sigreturn Dave Martin 2017-10-31 15:50 ` Dave Martin 2017-11-01 11:43 ` Catalin Marinas 2017-10-31 15:50 ` [PATCH v5 04/30] arm64: KVM: Hide unsupported AArch64 CPU features from guests Dave Martin 2017-11-01 4:47 ` Christoffer Dall 2017-11-01 10:26 ` Dave Martin 2017-11-02 8:15 ` Christoffer Dall 2017-11-02 9:20 ` Dave Martin 2017-11-02 11:01 ` Dave Martin 2017-11-02 19:18 ` Christoffer Dall 2017-10-31 15:50 ` [PATCH v5 05/30] arm64: efi: Add missing Kconfig dependency on KERNEL_MODE_NEON Dave Martin 2017-10-31 15:50 ` Dave Martin 2017-10-31 15:50 ` [PATCH v5 06/30] arm64: Port deprecated instruction emulation to new sysctl interface Dave Martin 2017-10-31 15:50 ` [PATCH v5 07/30] arm64: fpsimd: Simplify uses of {set,clear}_ti_thread_flag() Dave Martin 2017-10-31 15:51 ` [PATCH v5 08/30] arm64/sve: System register and exception syndrome definitions Dave Martin 2017-10-31 15:51 ` [PATCH v5 09/30] arm64/sve: Low-level SVE architectural state manipulation functions Dave Martin 2017-10-31 15:51 ` [PATCH v5 10/30] arm64/sve: Kconfig update and conditional compilation support Dave Martin 2017-10-31 15:51 ` [PATCH v5 11/30] arm64/sve: Signal frame and context structure definition Dave Martin 2017-11-08 16:34 ` Alex Bennée [this message] 2017-11-08 16:34 ` Alex Bennée 2017-10-31 15:51 ` [PATCH v5 12/30] arm64/sve: Low-level CPU setup Dave Martin 2017-11-08 16:37 ` Alex Bennée 2017-11-08 16:37 ` Alex Bennée 2017-10-31 15:51 ` [PATCH v5 13/30] arm64/sve: Core task context handling Dave Martin 2017-10-31 15:51 ` Dave Martin 2017-11-09 17:16 ` Alex Bennée 2017-11-09 17:16 ` Alex Bennée 2017-11-09 17:56 ` Dave Martin 2017-11-09 18:06 ` Alex Bennée 2017-11-09 18:06 ` Alex Bennée 2017-10-31 15:51 ` [PATCH v5 14/30] arm64/sve: Support vector length resetting for new processes Dave Martin 2017-10-31 15:51 ` [PATCH v5 15/30] arm64/sve: Signal handling support Dave Martin 2017-10-31 15:51 ` Dave Martin 2017-11-01 14:33 ` Catalin Marinas 2017-11-07 13:22 ` Alex Bennée 2017-11-07 13:22 ` Alex Bennée 2017-11-08 16:11 ` Dave Martin 2017-12-06 19:56 ` Kees Cook 2017-12-07 10:49 ` Will Deacon 2017-12-07 12:03 ` Dave Martin 2017-12-07 18:50 ` Kees Cook 2017-12-11 14:07 ` Will Deacon 2017-12-11 19:23 ` Kees Cook 2017-12-12 10:40 ` Will Deacon 2017-12-12 11:11 ` Dave Martin 2017-12-12 19:36 ` Kees Cook 2017-12-12 19:36 ` Kees Cook 2017-10-31 15:51 ` [PATCH v5 16/30] arm64/sve: Backend logic for setting the vector length Dave Martin 2017-10-31 15:51 ` Dave Martin 2017-11-10 10:27 ` Alex Bennée 2017-11-10 10:27 ` Alex Bennée 2017-10-31 15:51 ` [PATCH v5 17/30] arm64: cpufeature: Move sys_caps_initialised declarations Dave Martin 2017-10-31 15:51 ` [PATCH v5 18/30] arm64/sve: Probe SVE capabilities and usable vector lengths Dave Martin 2017-10-31 15:51 ` Dave Martin 2017-10-31 15:51 ` [PATCH v5 19/30] arm64/sve: Preserve SVE registers around kernel-mode NEON use Dave Martin 2017-10-31 15:51 ` [PATCH v5 20/30] arm64/sve: Preserve SVE registers around EFI runtime service calls Dave Martin 2017-10-31 15:51 ` [PATCH v5 21/30] arm64/sve: ptrace and ELF coredump support Dave Martin 2017-10-31 15:51 ` [PATCH v5 22/30] arm64/sve: Add prctl controls for userspace vector length management Dave Martin 2017-10-31 15:51 ` Dave Martin 2017-10-31 15:51 ` [PATCH v5 23/30] arm64/sve: Add sysctl to set the default vector length for new processes Dave Martin 2017-10-31 15:51 ` Dave Martin 2017-10-31 15:51 ` [PATCH v5 24/30] arm64/sve: KVM: Prevent guests from using SVE Dave Martin 2017-10-31 15:51 ` Dave Martin 2017-10-31 15:51 ` [PATCH v5 25/30] arm64/sve: KVM: Treat guest SVE use as undefined instruction execution Dave Martin 2017-10-31 15:51 ` [PATCH v5 26/30] arm64/sve: KVM: Hide SVE from CPU features exposed to guests Dave Martin 2017-10-31 15:51 ` [PATCH v5 27/30] arm64/sve: Detect SVE and activate runtime support Dave Martin 2017-10-31 15:51 ` Dave Martin 2017-10-31 15:51 ` [RFC PATCH v5 29/30] arm64: signal: Report signal frame size to userspace via auxv Dave Martin 2017-10-31 15:51 ` Dave Martin 2017-10-31 15:51 ` [RFC PATCH v5 30/30] arm64/sve: signal: Include SVE when computing AT_MINSIGSTKSZ Dave Martin 2017-10-31 15:51 ` Dave Martin [not found] ` <1509465082-30427-1-git-send-email-Dave.Martin-5wv7dgnIgG8@public.gmane.org> 2017-10-31 15:51 ` [PATCH v5 28/30] arm64/sve: Add documentation Dave Martin 2017-10-31 15:51 ` Dave Martin 2017-11-02 16:32 ` [PATCH v5 00/30] ARM Scalable Vector Extension (SVE) Will Deacon 2017-11-02 16:32 ` Will Deacon [not found] ` <20171102163248.GB595-5wv7dgnIgG8@public.gmane.org> 2017-11-02 17:04 ` Dave P Martin 2017-11-02 17:04 ` Dave P Martin 2017-11-29 15:04 ` Alex Bennée 2017-11-29 15:04 ` Alex Bennée [not found] ` <877eu9dt3n.fsf-QSEj5FYQhm4dnm+yROfE0A@public.gmane.org> 2017-11-29 15:21 ` Will Deacon 2017-11-29 15:21 ` Will Deacon [not found] ` <20171129152140.GD10650-5wv7dgnIgG8@public.gmane.org> 2017-11-29 15:37 ` Dave Martin 2017-11-29 15:37 ` Dave Martin 2018-01-08 14:49 ` Yury Norov 2018-01-08 14:49 ` Yury Norov 2018-01-09 16:51 ` Yury Norov 2018-01-09 16:51 ` Yury Norov 2018-01-15 17:22 ` Dave Martin 2018-01-15 17:22 ` Dave Martin [not found] ` <20180115172201.GW22781-M5GwZQ6tE7x5pKCnmE3YQBJ8xKzm50AiAL8bYrjMMd8@public.gmane.org> 2018-01-16 10:11 ` Yury Norov 2018-01-16 10:11 ` Yury Norov 2018-01-16 16:05 ` Dave Martin 2018-01-16 16:05 ` Dave Martin 2018-01-15 16:55 ` Dave Martin 2018-01-15 16:55 ` Dave Martin
Reply instructions: You may reply publicly to this message via plain-text email using any one of the following methods: * Save the following mbox file, import it into your mail client, and reply-to-all from there: mbox Avoid top-posting and favor interleaved quoting: https://en.wikipedia.org/wiki/Posting_style#Interleaved_style * Reply using the --to, --cc, and --in-reply-to switches of git-send-email(1): git send-email \ --in-reply-to=87fu9orapw.fsf@linaro.org \ --to=alex.bennee@linaro.org \ --cc=Dave.Martin@arm.com \ --cc=ard.biesheuvel@linaro.org \ --cc=catalin.marinas@arm.com \ --cc=kvmarm@lists.cs.columbia.edu \ --cc=libc-alpha@sourceware.org \ --cc=linux-arch@vger.kernel.org \ --cc=linux-arm-kernel@lists.infradead.org \ --cc=szabolcs.nagy@arm.com \ --cc=tokamoto@jp.fujitsu.com \ --cc=will.deacon@arm.com \ /path/to/YOUR_REPLY https://kernel.org/pub/software/scm/git/docs/git-send-email.html * If your mail client supports setting the In-Reply-To header via mailto: links, try the mailto: linkBe sure your reply has a Subject: header at the top and a blank line before the message body.
This is a public inbox, see mirroring instructions for how to clone and mirror all data and code used for this inbox; as well as URLs for NNTP newsgroup(s).