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From: "Arnd Bergmann" <arnd@arndb.de>
To: "Jonathan Cameron" <Jonathan.Cameron@huawei.com>
Cc: "Conor Dooley" <conor@kernel.org>,
	"Catalin Marinas" <catalin.marinas@arm.com>,
	linux-cxl@vger.kernel.org, linux-arm-kernel@lists.infradead.org,
	Linux-Arch <linux-arch@vger.kernel.org>,
	linux-mm@kvack.org, "Dan Williams" <dan.j.williams@intel.com>,
	"H. Peter Anvin" <hpa@zytor.com>,
	"Peter Zijlstra" <peterz@infradead.org>,
	"Andrew Morton" <akpm@linux-foundation.org>,
	"Drew Fustini" <fustini@kernel.org>,
	"Linus Walleij" <linus.walleij@linaro.org>,
	"Alexandre Belloni" <alexandre.belloni@bootlin.com>,
	"Krzysztof Kozlowski" <krzk@kernel.org>,
	"James Morse" <james.morse@arm.com>,
	"Will Deacon" <will@kernel.org>,
	"Davidlohr Bueso" <dave@stgolabs.net>,
	linuxarm@huawei.com, "Yushan Wang" <wangyushan12@huawei.com>,
	"Lorenzo Pieralisi" <lpieralisi@kernel.org>,
	"Mark Rutland" <mark.rutland@arm.com>,
	"Dave Hansen" <dave.hansen@linux.intel.com>,
	"Thomas Gleixner" <tglx@linutronix.de>,
	"Ingo Molnar" <mingo@redhat.com>,
	"Borislav Petkov" <bp@alien8.de>,
	x86@kernel.org, "Andy Lutomirski" <luto@kernel.org>,
	"Dave Jiang" <dave.jiang@intel.com>
Subject: Re: [PATCH v5 0/6]  Cache coherency management subsystem
Date: Fri, 14 Nov 2025 17:03:40 +0100	[thread overview]
Message-ID: <93c1c6be-dae5-477e-8924-1b77f8567732@app.fastmail.com> (raw)
In-Reply-To: <20251114155746.00003719@huawei.com>

On Fri, Nov 14, 2025, at 16:57, Jonathan Cameron wrote:
> On Fri, 14 Nov 2025 15:07:33 +0100 "Arnd Bergmann" <arnd@arndb.de> wrote:
> Hi Arnd,
>
> Thanks for taking another look.
>
> Agreed splitting the menus reduces chance of confusion, so makes
> sense to me as well.
>
> Implementation wise I think we have to use menuconfig + bool if we want
> to have help and dependencies and then an if block under that.
> The syntax for Kconfig always leaves me finding an example to copy
> rather than finding it intuitive
>
> menuconfig CACHEMAINT_FOR_DMA
> 	bool "Cache management for noncoherent DMA"
> 	depends on RISCV
> 	help
> 	  These drivers implement support for noncoherent DMA master devices
> 	  on platforms that lack the standard CPU interfaces for this.
>
> if CACHEMAINT_FOR_DMA
> ... drivers here...
>
> endif #CACHEMAINT_FOR_DMA
>
> menuconfig CACHEMAINT_FOR_HOTPLUG
> 	bool "Cache management for hotplug like operations"
> 	depends on GENERIC_CPU_CACHE_MAINTENANCE
> 	help
> 	   These drivers implement support for cache management flows
> 	   as required for action such as memory hotplug on platforms
> 	   where this is done by platform specific interfaces.
>
> if CACHEMAINT_FOR_HOTPLUG
> ... drivers here
>
> endif #CACHEMAINT_FOR_HOTPLUG

Works for me.

> I'm not sure if the 'hotplug like' is close enough to all the cases
> for device drivers that provide the services needed to implement
> ARCH_HAS_CPU_CACHE_INVALIDATE_MEMEGION

The _FOR_HOTPLUG does feel a little more specific than it should be,
but I haven't come up with a better name for it yet. We'll
probably figure that out if we ever get a second driver here.

> Alternative might be to phrase around pushing beyond the point of
> coherence, but that seems to be an ARM specific term and would
> seem to incorporate fine grained sharing where this interface might
> work but isn't a good solution.

Agreed.

     Arnd

      reply	other threads:[~2025-11-14 16:04 UTC|newest]

Thread overview: 13+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2025-10-31 11:17 [PATCH v5 0/6] Cache coherency management subsystem Jonathan Cameron
2025-10-31 11:17 ` [PATCH v5 1/6] memregion: Drop unused IORES_DESC_* parameter from cpu_cache_invalidate_memregion() Jonathan Cameron
2025-10-31 11:17 ` [PATCH v5 2/6] memregion: Support fine grained invalidate by cpu_cache_invalidate_memregion() Jonathan Cameron
2025-10-31 11:17 ` [PATCH v5 3/6] lib: Support ARCH_HAS_CPU_CACHE_INVALIDATE_MEMREGION Jonathan Cameron
2025-10-31 11:17 ` [PATCH v5 4/6] arm64: Select GENERIC_CPU_CACHE_MAINTENANCE Jonathan Cameron
2025-10-31 11:17 ` [PATCH v5 5/6] MAINTAINERS: Add Jonathan Cameron to drivers/cache and add lib/cache_maint.c + header Jonathan Cameron
2025-10-31 11:17 ` [PATCH v5 6/6] cache: Support cache maintenance for HiSilicon SoC Hydra Home Agent Jonathan Cameron
2025-11-08 20:02 ` [PATCH v5 0/6] Cache coherency management subsystem Conor Dooley
2025-11-14 12:49   ` Jonathan Cameron
2025-11-14 12:52     ` Conor Dooley
2025-11-14 14:07       ` Arnd Bergmann
2025-11-14 15:57         ` Jonathan Cameron
2025-11-14 16:03           ` Arnd Bergmann [this message]

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