From mboxrd@z Thu Jan 1 00:00:00 1970 From: Linus Torvalds Subject: Re: [PATCHv1, RFC 0/8] Boot-time switching between 4- and 5-level paging Date: Fri, 26 May 2017 08:51:48 -0700 Message-ID: References: <20170525203334.867-1-kirill.shutemov@linux.intel.com> <20170526130057.t7zsynihkdtsepkf@node.shutemov.name> Mime-Version: 1.0 Content-Type: text/plain; charset="UTF-8" Return-path: In-Reply-To: <20170526130057.t7zsynihkdtsepkf@node.shutemov.name> Sender: owner-linux-mm@kvack.org To: "Kirill A. Shutemov" Cc: "Kirill A. Shutemov" , Andrew Morton , the arch/x86 maintainers , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Andi Kleen , Dave Hansen , Andy Lutomirski , "linux-arch@vger.kernel.org" , linux-mm , Linux Kernel Mailing List List-Id: linux-arch.vger.kernel.org On Fri, May 26, 2017 at 6:00 AM, Kirill A. Shutemov wrote: > > I don't see how kernel threads can use 4-level paging. It doesn't work > from virtual memory layout POV. Kernel claims half of full virtual address > space for itself -- 256 PGD entries, not one as we would effectively have > in case of switching to 4-level paging. For instance, addresses, where > vmalloc and vmemmap are mapped, are not canonical with 4-level paging. I would have just assumed we'd map the kernel in the shared part that fits in the top 47 bits. But it sounds like you can't switch back and forth anyway, so I guess it's moot. Where *is* the LA57 documentation, btw? I had an old x86 architecture manual, so I updated it, but LA57 isn't mentioned in the new one either. Linus -- To unsubscribe, send a message with 'unsubscribe linux-mm' in the body to majordomo@kvack.org. For more info on Linux MM, see: http://www.linux-mm.org/ . Don't email: email@kvack.org From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-io0-f177.google.com ([209.85.223.177]:34355 "EHLO mail-io0-f177.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S934666AbdEZPvu (ORCPT ); Fri, 26 May 2017 11:51:50 -0400 MIME-Version: 1.0 In-Reply-To: <20170526130057.t7zsynihkdtsepkf@node.shutemov.name> References: <20170525203334.867-1-kirill.shutemov@linux.intel.com> <20170526130057.t7zsynihkdtsepkf@node.shutemov.name> From: Linus Torvalds Date: Fri, 26 May 2017 08:51:48 -0700 Message-ID: Subject: Re: [PATCHv1, RFC 0/8] Boot-time switching between 4- and 5-level paging Content-Type: text/plain; charset="UTF-8" Sender: linux-arch-owner@vger.kernel.org List-ID: To: "Kirill A. Shutemov" Cc: "Kirill A. Shutemov" , Andrew Morton , the arch/x86 maintainers , Thomas Gleixner , Ingo Molnar , "H. Peter Anvin" , Andi Kleen , Dave Hansen , Andy Lutomirski , "linux-arch@vger.kernel.org" , linux-mm , Linux Kernel Mailing List Message-ID: <20170526155148.Fuc39ttMebpfgw9YIG6I4Uwy2egtayLIx_Ari6ZJi8I@z> On Fri, May 26, 2017 at 6:00 AM, Kirill A. Shutemov wrote: > > I don't see how kernel threads can use 4-level paging. It doesn't work > from virtual memory layout POV. Kernel claims half of full virtual address > space for itself -- 256 PGD entries, not one as we would effectively have > in case of switching to 4-level paging. For instance, addresses, where > vmalloc and vmemmap are mapped, are not canonical with 4-level paging. I would have just assumed we'd map the kernel in the shared part that fits in the top 47 bits. But it sounds like you can't switch back and forth anyway, so I guess it's moot. Where *is* the LA57 documentation, btw? I had an old x86 architecture manual, so I updated it, but LA57 isn't mentioned in the new one either. Linus