From mboxrd@z Thu Jan 1 00:00:00 1970 From: Andy Lutomirski Subject: Re: [RFC PATCH v1 01/18] x86: Set the write-protect cache mode for AMD processors Date: Wed, 27 Apr 2016 07:33:21 -0700 Message-ID: References: <20160426225553.13567.19459.stgit@tlendack-t1.amdoffice.net> <20160426225604.13567.55443.stgit@tlendack-t1.amdoffice.net> Mime-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Transfer-Encoding: 7bit Return-path: In-Reply-To: <20160426225604.13567.55443.stgit-qCXWGYdRb2BnqfbPTmsdiZQ+2ll4COg0XqFh9Ls21Oc@public.gmane.org> List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , Sender: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org Errors-To: iommu-bounces-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org To: Tom Lendacky Cc: "linux-efi-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , kvm list , =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , Matt Fleming , X86 ML , "linux-mm-Bw31MaZKKs3YtjvyW6yDsg@public.gmane.org" , Alexander Potapenko , "H. Peter Anvin" , linux-arch , Jonathan Corbet , "linux-doc-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , kasan-dev , Ingo Molnar , Andrey Ryabinin , Arnd Bergmann , Borislav Petkov , Thomas Gleixner , Dmitry Vyukov , "linux-kernel-u79uwXL29TY76Z2rM5mHXA@public.gmane.org" , iommu-cunTk1MwBs9QetFLy7KEm3xJsTq8ys+cHZ5vskTnxNA@public.gmane.org, Paolo Bonzini List-Id: linux-arch.vger.kernel.org On Tue, Apr 26, 2016 at 3:56 PM, Tom Lendacky wrote: > For AMD processors that support PAT, set the write-protect cache mode > (_PAGE_CACHE_MODE_WP) entry to the actual write-protect value (x05). What's the purpose of using the WP memory type? --Andy From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-ob0-f172.google.com ([209.85.214.172]:36421 "EHLO mail-ob0-f172.google.com" rhost-flags-OK-OK-OK-OK) by vger.kernel.org with ESMTP id S1752755AbcD0Odl (ORCPT ); Wed, 27 Apr 2016 10:33:41 -0400 Received: by mail-ob0-f172.google.com with SMTP id j9so23450874obd.3 for ; Wed, 27 Apr 2016 07:33:41 -0700 (PDT) MIME-Version: 1.0 In-Reply-To: <20160426225604.13567.55443.stgit@tlendack-t1.amdoffice.net> References: <20160426225553.13567.19459.stgit@tlendack-t1.amdoffice.net> <20160426225604.13567.55443.stgit@tlendack-t1.amdoffice.net> From: Andy Lutomirski Date: Wed, 27 Apr 2016 07:33:21 -0700 Message-ID: Subject: Re: [RFC PATCH v1 01/18] x86: Set the write-protect cache mode for AMD processors Content-Type: text/plain; charset=UTF-8 Sender: linux-arch-owner@vger.kernel.org List-ID: To: Tom Lendacky Cc: linux-arch , "linux-efi@vger.kernel.org" , kvm list , "linux-doc@vger.kernel.org" , X86 ML , "linux-kernel@vger.kernel.org" , kasan-dev , "linux-mm@kvack.org" , iommu@lists.linux-foundation.org, =?UTF-8?B?UmFkaW0gS3LEjW3DocWZ?= , Arnd Bergmann , Jonathan Corbet , Matt Fleming , Joerg Roedel , Konrad Rzeszutek Wilk , Paolo Bonzini , Ingo Molnar , Borislav Petkov , "H. Peter Anvin" , Andrey Ryabinin , Alexander Potapenko , Thomas Gleixner , Dmitry Vyukov Message-ID: <20160427143321.w2UBzkj8ngx8ngbBMf73ZOuTyL92mU5dPdPC9qvaySs@z> On Tue, Apr 26, 2016 at 3:56 PM, Tom Lendacky wrote: > For AMD processors that support PAT, set the write-protect cache mode > (_PAGE_CACHE_MODE_WP) entry to the actual write-protect value (x05). What's the purpose of using the WP memory type? --Andy